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[Hexagon] Some cleanup of instruction selection code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235552 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
2015-04-22 21:17:00 +00:00
parent de3495610d
commit bbe056c9bc
11 changed files with 723 additions and 813 deletions
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2
test/CodeGen/Hexagon/BranchPredict.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; RUN: llc -march=hexagon -ifcvt-limit=0 < %s | FileCheck %s
; Check if the branch probabilities are reflected in the instructions:
; The basic block placement pass should place the more probable successor

2
test/CodeGen/Hexagon/adde.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: r{{[0-9]+:[0-9]+}} = #1
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})

8
test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll
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@ -1,8 +1,10 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= lsr(r{{[0-9]+}}:{{[0-9]+}}, #4)
; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= lsr(r{{[0-9]+}}:{{[0-9]+}}, #2)
; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
; CHECK-DAG: ct0({{r[0-9]*:[0-9]*}})
; CHECK-DAG: cl0({{r[0-9]*:[0-9]*}})
; CHECK-DAG: ct0({{r[0-9]*}})
; CHECK-DAG: cl0({{r[0-9]*}})
; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
define i32 @foo(i64 %a, i32 %b) nounwind {
entry:

2
test/CodeGen/Hexagon/macint.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we generate integer multiply accumulate.
; CHECK: r{{[0-9]+}} += mpyi(r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}},
define i32 @main(i32* %a, i32* %b) nounwind {
entry:

17
test/CodeGen/Hexagon/newvaluejump2.ll
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@ -1,17 +1,16 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
; RUN: | FileCheck %s
; Check that we generate new value jump, both registers, with one
; of the registers as new.
@Reg = common global i8 0, align 1
@Reg = common global i32 0, align 4
define i32 @main() nounwind {
entry:
; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
%Reg2 = alloca i8, align 1
%0 = load i8, i8* %Reg2, align 1
%conv0 = zext i8 %0 to i32
%1 = load i8, i8* @Reg, align 1
%conv1 = zext i8 %1 to i32
%tobool = icmp sle i32 %conv0, %conv1
; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
%Reg2 = alloca i32, align 4
%0 = load i32, i32* %Reg2, align 4
%1 = load i32, i32* @Reg, align 4
%tobool = icmp sle i32 %0, %1
br i1 %tobool, label %if.then, label %if.else
if.then:

2
test/CodeGen/Hexagon/sube.ll
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@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: r{{[0-9]+:[0-9]+}} = #1
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})