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Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using

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the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114473 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2010-09-21 20:42:50 +00:00
parent 78d3af47f5
commit bc146b0a4d
3 changed files with 29 additions and 23 deletions
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14
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -1424,6 +1424,20 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
N0.getOperand(0).getOperand(1),
N0.getOperand(1)));
if (N1.getOpcode() == ISD::AND) {
SDValue AndOp0 = N1.getOperand(0);
ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
unsigned DestBits = VT.getScalarType().getSizeInBits();
// (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
// and similar xforms where the inner op is either ~0 or 0.
if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
DebugLoc DL = N->getDebugLoc();
return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
}
}
return SDValue();
}