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Fix instruction encoding for "isel" on PowerPC,

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using a new instruction format AForm_4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2012-11-13 19:14:19 +00:00
parent 2adc503f29
commit bc40df3f22
3 changed files with 22 additions and 2 deletions
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2
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -511,7 +511,7 @@ def RLWINM8 : MForm_2<21,
"rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
[]>;
def ISEL8 : AForm_1<31, 15,
def ISEL8 : AForm_4<31, 15,
(outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB, pred:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral,
[]>;

20
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -758,6 +758,26 @@ class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
let FRB = 0;
}
class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12).
bits<3> CR;
let Pattern = pattern;
let Inst{6-10} = RT;
let Inst{11-15} = RA;
let Inst{16-20} = RB;
let Inst{21-23} = CR;
let Inst{24-25} = BIBO{6-5};
let Inst{26-30} = xo;
let Inst{31} = 0;
}
// 1.7.13 M-Form
class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>

2
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1414,7 +1414,7 @@ let Uses = [RM] in {
}
let PPC970_Unit = 1 in { // FXU Operations.
def ISEL : AForm_1<31, 15,
def ISEL : AForm_4<31, 15,
(outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral,
[]>;