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Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:

Browse Source 
_test:
        lis r2, 743
        li r3, 0
        stw r3, 32751(r2)
        blr

instead of:

_test:
        li r2, 0
        stw r2, 32751(48693248)
        blr

Implement support for ppc64 as well, allowing it to produce better code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-02-17 06:44:03 +00:00
parent 6e1472a928
commit bc681d6af4
1 changed files with 9 additions and 5 deletions
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14
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -743,14 +743,18 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
return true;
}
// FIXME: Handle small sext constant offsets in PPC64 mode also!
if (CN->getValueType(0) == MVT::i32) {
// Handle 32-bit sext immediates with LIS + addr mode.
if (CN->getValueType(0) == MVT::i32 ||
(int64_t)CN->getValue() == (int)CN->getValue()) {
int Addr = (int)CN->getValue();
// Otherwise, break this down into an LIS + disp.
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
return true;
}
}