mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-21 03:32:29 +00:00
Move code around. No functionality changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135657 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
67727cac2f
commit
bca4781b61
@ -5289,8 +5289,10 @@ defm : pclmul_alias<"lqlq", 0x00>;
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// AVX Instructions
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//===----------------------------------------------------------------------===//
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// Load from memory and broadcast to all elements of the destination operand
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//===----------------------------------------------------------------------===//
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// VBROADCAST - Load from memory and broadcast to all elements of the
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// destination operand
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//
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class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic Int> :
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AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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@ -5306,7 +5308,12 @@ def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
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def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
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int_x86_avx_vbroadcastf128_pd_256>;
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// Insert packed floating-point values
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def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
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(VBROADCASTF128 addr:$src)>;
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//===----------------------------------------------------------------------===//
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// VINSERTF128 - Insert packed floating-point values
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//
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def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR128:$src2, i8imm:$src3),
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"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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@ -5316,7 +5323,33 @@ def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
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"vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, VEX_4V;
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// Extract packed floating-point values
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def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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//===----------------------------------------------------------------------===//
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// VEXTRACTF128 - Extract packed floating-point values
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//
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def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
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(ins VR256:$src1, i8imm:$src2),
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"vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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@ -5326,7 +5359,33 @@ def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
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"vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, VEX;
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// Conditional SIMD Packed Loads and Stores
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def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4f32 (VEXTRACTF128rr
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(v8f32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2f64 (VEXTRACTF128rr
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(v4f64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4i32 (VEXTRACTF128rr
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(v8i32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2i64 (VEXTRACTF128rr
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(v4i64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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//===----------------------------------------------------------------------===//
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// VMASKMOV - Conditional SIMD Packed Loads and Stores
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//
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multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
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Intrinsic IntLd, Intrinsic IntLd256,
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Intrinsic IntSt, Intrinsic IntSt256,
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@ -5364,7 +5423,9 @@ defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
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int_x86_avx_maskstore_pd_256,
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memopv2f64, memopv4f64>;
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// Permute Floating-Point Values
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//===----------------------------------------------------------------------===//
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// VPERM - Permute Floating-Point Values
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//
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multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop_f,
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X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
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@ -5414,65 +5475,6 @@ def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
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"vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, VEX_4V;
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// Zero All YMM registers
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def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
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[(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
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// Zero Upper bits of YMM registers
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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[(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
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def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4f32 (VEXTRACTF128rr
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(v8f32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2f64 (VEXTRACTF128rr
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(v4f64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4i32 (VEXTRACTF128rr
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(v8i32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2i64 (VEXTRACTF128rr
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(v4i64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
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(VBROADCASTF128 addr:$src)>;
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def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
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(VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
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def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
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@ -5490,6 +5492,17 @@ def : Pat<(int_x86_avx_vperm2f128_si_256
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VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
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(VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
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//===----------------------------------------------------------------------===//
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// VZERO - Zero YMM registers
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//
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// Zero All YMM registers
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def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
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[(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
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// Zero Upper bits of YMM registers
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def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
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[(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
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//===----------------------------------------------------------------------===//
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// SSE Shuffle pattern fragments
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//===----------------------------------------------------------------------===//
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