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Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-06-19 06:10:58 +00:00
parent 64429cefba
commit bd01df2487
15 changed files with 26 additions and 47 deletions
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7
include/llvm/Support/StreamableMemoryObject.h
View File

@ -13,6 +13,7 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/DataStream.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MemoryObject.h"
#include <cassert>
#include <memory>
@ -115,7 +116,7 @@ public:
// requiring that the bitcode size be known, or otherwise ensuring that
// the memory doesn't go away/get reallocated, but it's
// not currently necessary. Users that need the pointer don't stream.
assert(0 && "getPointer in streaming memory objects not allowed");
llvm_unreachable("getPointer in streaming memory objects not allowed");
return nullptr;
}
bool isValidAddress(uint64_t address) const override;
@ -154,8 +155,8 @@ private:
kChunkSize);
BytesRead += bytes;
if (bytes < kChunkSize) {
if (ObjectSize && BytesRead < Pos)
assert(0 && "Unexpected short read fetching bitcode");
assert((!ObjectSize || BytesRead >= Pos) &&
"Unexpected short read fetching bitcode");
if (BytesRead <= Pos) { // reached EOF/ran out of bytes
ObjectSize = BytesRead;
EOFReached = true;

3
lib/MC/ELFObjectWriter.cpp
View File

@ -1574,8 +1574,7 @@ void ELFObjectWriter::WriteSection(MCAssembler &Asm,
break;
default:
assert(0 && "FIXME: sh_type value not supported!");
break;
llvm_unreachable("FIXME: sh_type value not supported!");
}
if (TargetObjectWriter->getEMachine() == ELF::EM_ARM &&

10
lib/TableGen/Record.cpp
View File

@ -811,20 +811,14 @@ Init *UnOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) const {
}
case HEAD: {
if (ListInit *LHSl = dyn_cast<ListInit>(LHS)) {
if (LHSl->getSize() == 0) {
assert(0 && "Empty list in car");
return nullptr;
}
assert(LHSl->getSize() != 0 && "Empty list in car");
return LHSl->getElement(0);
}
break;
}
case TAIL: {
if (ListInit *LHSl = dyn_cast<ListInit>(LHS)) {
if (LHSl->getSize() == 0) {
assert(0 && "Empty list in cdr");
return nullptr;
}
assert(LHSl->getSize() != 0 && "Empty list in cdr");
// Note the +1. We can't just pass the result of getValues()
// directly.
ArrayRef<Init *>::iterator begin = LHSl->getValues().begin()+1;

4
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -823,8 +823,7 @@ AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
#ifndef NDEBUG
MI->dump();
#endif
assert(0 && "Unexpected instruction for custom inserter!");
break;
llvm_unreachable("Unexpected instruction for custom inserter!");
case AArch64::F128CSEL:
return EmitF128CSEL(MI, BB);
@ -833,7 +832,6 @@ AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case TargetOpcode::PATCHPOINT:
return emitPatchPoint(MI, BB);
}
llvm_unreachable("Unexpected instruction for custom inserter!");
}
//===----------------------------------------------------------------------===//

3
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -3447,8 +3447,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
case Match_MnemonicFail:
return Error(Loc, "unrecognized instruction mnemonic");
default:
assert(0 && "unexpected error code!");
return Error(Loc, "invalid instruction format");
llvm_unreachable("unexpected error code!");
}
}

3
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
View File

@ -37,8 +37,7 @@ getVariant(uint64_t LLVMDisassembler_VariantKind) {
case LLVMDisassembler_VariantKind_ARM64_TLVP:
case LLVMDisassembler_VariantKind_ARM64_TLVOFF:
default:
assert(0 && "bad LLVMDisassembler_VariantKind");
return MCSymbolRefExpr::VK_None;
llvm_unreachable("bad LLVMDisassembler_VariantKind");
}
}

8
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
View File

@ -218,13 +218,9 @@ AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
const MCSubtargetInfo &STI) const {
if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
else {
assert(MO.isImm() && "did not expect relocated expression");
return static_cast<unsigned>(MO.getImm());
}
assert(0 && "Unable to encode MCOperand!");
return 0;
assert(MO.isImm() && "did not expect relocated expression");
return static_cast<unsigned>(MO.getImm());
}
template<unsigned FixupKind> uint32_t

3
lib/Target/ARM/A15SDOptimizer.cpp
View File

@ -321,8 +321,7 @@ unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
}
assert(0 && "Unhandled update pattern!");
return 0;
llvm_unreachable("Unhandled update pattern!");
}
// Return true if this MachineInstr inserts a scalar (SPR) value into

3
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -1047,8 +1047,7 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
// we have a movt or a movw, but that led to misleadingly results.
// This is now disallowed in the the AsmParser in validateInstruction()
// so this should never happen.
assert(0 && "expression without :upper16: or :lower16:");
return 0;
llvm_unreachable("expression without :upper16: or :lower16:");
}
uint32_t ARMMCCodeEmitter::

7
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1538,14 +1538,13 @@ int HexagonInstrInfo::GetDotOldOp(const int opc) const {
int NewOp = opc;
if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
NewOp = Hexagon::getPredOldOpcode(NewOp);
if (NewOp < 0)
assert(0 && "Couldn't change predicate new instruction to its old form.");
assert(NewOp >= 0 &&
"Couldn't change predicate new instruction to its old form.");
}
if (isNewValueStore(NewOp)) { // Convert into non-new-value format
NewOp = Hexagon::getNonNVStore(NewOp);
if (NewOp < 0)
assert(0 && "Couldn't change new-value store to its old form.");
assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
}
return NewOp;
}

2
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
View File

@ -65,7 +65,7 @@ public:
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const override {
// FIXME.
assert(0 && "RelaxInstruction() unimplemented");
llvm_unreachable("RelaxInstruction() unimplemented");
return false;
}

14
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@ -172,17 +172,13 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixup,
const MCSubtargetInfo &STI) const {
if (MO.isReg()) {
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
return MRI.getEncodingValue(MO.getReg());
} else {
return getHWReg(MO.getReg());
}
} else if (MO.isImm()) {
return MO.getImm();
} else {
assert(0);
return 0;
return getHWReg(MO.getReg());
}
assert(MO.isImm());
return MO.getImm();
}
#include "AMDGPUGenMCCodeEmitter.inc"

2
lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
View File

@ -173,6 +173,6 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
raw_ostream &O)
{
assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");
llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
return true;
}

2
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
View File

@ -196,7 +196,7 @@ namespace {
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const override {
// FIXME.
assert(0 && "fixupNeedsRelaxation() unimplemented");
llvm_unreachable("fixupNeedsRelaxation() unimplemented");
return false;
}
void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {

2
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
View File

@ -133,7 +133,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
if (Expr->EvaluateAsAbsolute(Res))
return Res;
assert(0 && "Unhandled expression!");
llvm_unreachable("Unhandled expression!");
return 0;
}