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Remove getSubtargetImpl from AArch64ISelLowering and cache the

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correct subtarget by passing it in during the constructor as
TargetLowering is Subtarget specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227402 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-01-29 00:19:42 +00:00
parent 3dd7e82123
commit bd2a700208
3 changed files with 10 additions and 13 deletions
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18
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -67,10 +67,9 @@ EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
cl::desc("Allow AArch64 SLI/SRI formation"), cl::desc("Allow AArch64 SLI/SRI formation"),
cl::init(false)); cl::init(false));
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM) const AArch64Subtarget &STI)
: TargetLowering(TM) { : TargetLowering(TM), Subtarget(&STI) {
Subtarget = &TM.getSubtarget<AArch64Subtarget>();
// AArch64 doesn't have comparisons which set GPRs or setcc instructions, so // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
// we have to make something up. Arbitrarily, choose ZeroOrOne. // we have to make something up. Arbitrarily, choose ZeroOrOne.
@ -879,7 +878,7 @@ AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
// Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB] // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
MachineFunction *MF = MBB->getParent(); MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); const TargetInstrInfo *TII = Subtarget->getInstrInfo();
const BasicBlock *LLVM_BB = MBB->getBasicBlock(); const BasicBlock *LLVM_BB = MBB->getBasicBlock();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
MachineFunction::iterator It = MBB; MachineFunction::iterator It = MBB;
@ -2796,8 +2795,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
// Add a register mask operand representing the call-preserved registers. // Add a register mask operand representing the call-preserved registers.
const uint32_t *Mask; const uint32_t *Mask;
const AArch64RegisterInfo *TRI = static_cast<const AArch64RegisterInfo *>( const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
MF.getSubtarget().getRegisterInfo());
if (IsThisReturn) { if (IsThisReturn) {
// For 'this' returns, use the X0-preserving mask if applicable // For 'this' returns, use the X0-preserving mask if applicable
Mask = TRI->getThisReturnPreservedMask(CallConv); Mask = TRI->getThisReturnPreservedMask(CallConv);
@ -3027,8 +3025,7 @@ AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
// trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
// silly). // silly).
const uint32_t *Mask = const uint32_t *Mask =
static_cast<const AArch64RegisterInfo *>( Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
DAG.getSubtarget().getRegisterInfo())->getTLSCallPreservedMask();
// Finally, we can make the call. This is just a degenerate version of a // Finally, we can make the call. This is just a degenerate version of a
// normal AArch64 call node: x0 takes the address of the descriptor, and // normal AArch64 call node: x0 takes the address of the descriptor, and
@ -3076,8 +3073,7 @@ SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
// trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
// silly). // silly).
const uint32_t *Mask = const uint32_t *Mask =
static_cast<const AArch64RegisterInfo *>( Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
DAG.getSubtarget().getRegisterInfo())->getTLSCallPreservedMask();
// The function takes only one argument: the address of the descriptor itself // The function takes only one argument: the address of the descriptor itself
// in X0. // in X0.

3
lib/Target/AArch64/AArch64ISelLowering.h
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@ -207,7 +207,8 @@ class AArch64TargetLowering : public TargetLowering {
bool RequireStrictAlign; bool RequireStrictAlign;
public: public:
explicit AArch64TargetLowering(const TargetMachine &TM); explicit AArch64TargetLowering(const TargetMachine &TM,
const AArch64Subtarget &STI);
/// Selects the correct CCAssignFn for a given CallingConvention value. /// Selects the correct CCAssignFn for a given CallingConvention value.
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;

2
lib/Target/AArch64/AArch64Subtarget.cpp
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@ -51,7 +51,7 @@ AArch64Subtarget::AArch64Subtarget(const std::string &TT,
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(), IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)), InstrInfo(initializeSubtargetDependencies(FS)),
TSInfo(TM.getDataLayout()), TLInfo(TM) {} TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
/// ClassifyGlobalReference - Find the target operand flags that describe /// ClassifyGlobalReference - Find the target operand flags that describe
/// how a global value should be referenced for the current subtarget. /// how a global value should be referenced for the current subtarget.