diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 6ba236c0ff0..204b2eb8568 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -145,12 +145,8 @@ public:
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(MVT::Other);
     VTs.push_back(MVT::Flag);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(Chain);
-    Ops.push_back(getRegister(Reg, N.getValueType()));
-    Ops.push_back(N);
-    if (Flag.Val) Ops.push_back(Flag);
-    return getNode(ISD::CopyToReg, VTs, Ops);
+    SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
+    return getNode(ISD::CopyToReg, VTs, Ops, Flag.Val ? 4 : 3);
   }
 
   // Similar to last getCopyToReg() except parameter Reg is a SDOperand
@@ -159,12 +155,8 @@ public:
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(MVT::Other);
     VTs.push_back(MVT::Flag);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(Chain);
-    Ops.push_back(Reg);
-    Ops.push_back(N);
-    if (Flag.Val) Ops.push_back(Flag);
-    return getNode(ISD::CopyToReg, VTs, Ops);
+    SDOperand Ops[] = { Chain, Reg, N, Flag };
+    return getNode(ISD::CopyToReg, VTs, Ops, Flag.Val ? 4 : 3);
   }
   
   SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
@@ -218,14 +210,17 @@ public:
                     SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
                     SDOperand N5);
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
-                    std::vector<SDOperand> &Children);
-  SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
-                    std::vector<SDOperand> &Ops);
-
+                    const SDOperand *Ops, unsigned NumOps);
   SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
-                    const SDOperand *Ops, unsigned NumOps);
+                    const std::vector<SDOperand> &Ops) {
+    return getNode(Opcode, VT, &Ops[0], Ops.size());
+  }
   SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
                     const SDOperand *Ops, unsigned NumOps);
+  SDOperand getNode(unsigned Opcode, std::vector<MVT::ValueType> &ResultTys,
+                    const std::vector<SDOperand> &Ops) {
+    return getNode(Opcode, ResultTys, &Ops[0], Ops.size());
+  }
   
   
   /// getSetCC - Helper function to make it easier to build SetCC's if you just
@@ -351,7 +346,7 @@ public:
                         SDOperand Op4, SDOperand Op5, SDOperand Op6,
                         SDOperand Op7, SDOperand Op8);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
-                        std::vector<SDOperand> &Ops);
+                        const SDOperand *Ops, unsigned NumOps);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                         MVT::ValueType VT2, SDOperand Op1);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
@@ -391,7 +386,8 @@ public:
                         SDOperand Op3, SDOperand Op4, SDOperand Op5,
                         SDOperand Op6, SDOperand Op7);
   SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1, 
-                        MVT::ValueType VT2, std::vector<SDOperand> &Ops);
+                        MVT::ValueType VT2,
+                        const SDOperand *Ops, unsigned NumOps);
   
   /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
   /// This can cause recursive merging of nodes in the DAG.  Use the first
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a767cd971ea..aa325b3ba40 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -510,7 +510,7 @@ SDOperand DAGCombiner::visit(SDNode *N) {
 }
 
 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   bool Changed = false;
 
   // If the token factor has two operands and one is the entry token, replace
@@ -539,7 +539,7 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
     }
   }
   if (Changed)
-    return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
+    return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
   return SDOperand();
 }
 
@@ -1284,7 +1284,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
       // Produce a vector of zeros.
       SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
       std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
-      return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+      return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
     }
   }
   
@@ -1953,14 +1953,14 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   // If this is a conversion of N elements of one type to N elements of another
   // type, convert each element.  This handles FP<->INT cases.
   if (SrcBitSize == DstBitSize) {
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
       AddToWorkList(Ops.back().Val);
     }
     Ops.push_back(*(BV->op_end()-2)); // Add num elements.
     Ops.push_back(DAG.getValueType(DstEltVT));
-    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
   }
   
   // Otherwise, we're growing or shrinking the elements.  To avoid having to
@@ -1992,7 +1992,7 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   if (SrcBitSize < DstBitSize) {
     unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
     
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
          i += NumInputsPerOutput) {
       bool isLE = TLI.isLittleEndian();
@@ -2016,13 +2016,13 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
 
     Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
     Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
-    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
   }
   
   // Finally, this must be the case where we are shrinking elements: each input
   // turns into multiple outputs.
   unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
     if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
       for (unsigned j = 0; j != NumOutputsPerInput; ++j)
@@ -2043,7 +2043,7 @@ ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
   }
   Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
   Ops.push_back(DAG.getValueType(DstEltVT));            // Add element size.
-  return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
 }
 
 
@@ -2448,10 +2448,11 @@ SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
     if (Elt < Ops.size())
       Ops[Elt] = InVal;
-    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+    return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
+                       &Ops[0], Ops.size());
   }
   
   return SDOperand();
@@ -2468,10 +2469,11 @@ SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
     if (Elt < Ops.size()-2)
       Ops[Elt] = InVal;
-    return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+    return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
+                       &Ops[0], Ops.size());
   }
   
   return SDOperand();
@@ -2524,7 +2526,7 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
   
   // If everything is good, we can make a shuffle operation.
   if (VecIn1.Val) {
-    std::vector<SDOperand> BuildVecIndices;
+    SmallVector<SDOperand, 8> BuildVecIndices;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
         BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
@@ -2549,10 +2551,10 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
     BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
     
     // Return the new VVECTOR_SHUFFLE node.
-    std::vector<SDOperand> Ops;
-    Ops.push_back(VecIn1);
+    SDOperand Ops[5];
+    Ops[0] = VecIn1;
     if (VecIn2.Val) {
-      Ops.push_back(VecIn2);
+      Ops[1] = VecIn2;
     } else {
        // Use an undef vbuild_vector as input for the second operand.
       std::vector<SDOperand> UnOps(NumInScalars,
@@ -2560,13 +2562,15 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
                                            cast<VTSDNode>(EltType)->getVT()));
       UnOps.push_back(NumElts);
       UnOps.push_back(EltType);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
-      AddToWorkList(Ops.back().Val);
+      Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                           &UnOps[0], UnOps.size());
+      AddToWorkList(Ops[1].Val);
     }
-    Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
-    Ops.push_back(NumElts);
-    Ops.push_back(EltType);
-    return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+    Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                         &BuildVecIndices[0], BuildVecIndices.size());
+    Ops[3] = NumElts;
+    Ops[4] = EltType;
+    return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
   }
   
   return SDOperand();
@@ -2668,7 +2672,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       return DAG.getNode(ISD::UNDEF, N->getValueType(0));
     // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
     // first operand.
-    std::vector<SDOperand> MappedOps;
+    SmallVector<SDOperand, 8> MappedOps;
     for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
       if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2680,7 +2684,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       }
     }
     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
-                           MappedOps);
+                           &MappedOps[0], MappedOps.size());
     AddToWorkList(ShufMask.Val);
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
                        N0, 
@@ -2785,7 +2789,7 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
   if (isUnary || N0 == N1) {
     // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
     // first operand.
-    std::vector<SDOperand> MappedOps;
+    SmallVector<SDOperand, 8> MappedOps;
     for (unsigned i = 0; i != NumElts; ++i) {
       if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2801,7 +2805,7 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
     MappedOps.push_back(ShufMask.getOperand(NumElts+1));
 
     ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
-                           MappedOps);
+                           &MappedOps[0], MappedOps.size());
     AddToWorkList(ShufMask.Val);
     
     // Build the undef vector.
@@ -2810,7 +2814,8 @@ SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
       MappedOps[i] = UDVal;
     MappedOps[NumElts  ] = *(N0.Val->op_end()-2);
     MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
-    UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
+    UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                        &MappedOps[0], MappedOps.size());
     
     return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 
                        N0, UDVal, ShufMask,
@@ -2863,13 +2868,16 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
       std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
       ZeroOps.push_back(NumEltsNode);
       ZeroOps.push_back(EVTNode);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
+      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                                &ZeroOps[0], ZeroOps.size()));
       IdxOps.push_back(NumEltsNode);
       IdxOps.push_back(EVTNode);
-      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
+      Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                                &IdxOps[0], IdxOps.size()));
       Ops.push_back(NumEltsNode);
       Ops.push_back(EVTNode);
-      SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+      SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+                                     &Ops[0], Ops.size());
       if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
         Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
                              DstVecSize, DstVecEVT);
@@ -2896,7 +2904,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
   // this operation.
   if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 
       RHS.getOpcode() == ISD::VBUILD_VECTOR) {
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
       SDOperand LHSOp = LHS.getOperand(i);
       SDOperand RHSOp = RHS.getOperand(i);
@@ -2927,7 +2935,7 @@ SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
     if (Ops.size() == LHS.getNumOperands()-2) {
       Ops.push_back(*(LHS.Val->op_end()-2));
       Ops.push_back(*(LHS.Val->op_end()-1));
-      return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+      return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
     }
   }
   
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 22f6c7c0741..906d71849ed 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -241,7 +241,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
     assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
     if (NumEltsGrowth > 1) {
       // Renumber the elements.
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
         SDOperand InOp = Mask.getOperand(i);
         for (unsigned j = 0; j != NumEltsGrowth; ++j) {
@@ -253,7 +253,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
           }
         }
       }
-      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
+      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
     }
     VT = NVT;
     break;
@@ -666,7 +666,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           cast<StringSDNode>(Node->getOperand(4))->getValue();
         unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
 
-        std::vector<SDOperand> Ops;
+        SmallVector<SDOperand, 8> Ops;
         Ops.push_back(Tmp1);  // chain
         SDOperand LineOp = Node->getOperand(1);
         SDOperand ColOp = Node->getOperand(2);
@@ -675,13 +675,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           Ops.push_back(LineOp);  // line #
           Ops.push_back(ColOp);  // col #
           Ops.push_back(DAG.getConstant(SrcFile, MVT::i32));  // source file id
-          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
         } else {
           unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
           unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
           unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
           Ops.push_back(DAG.getConstant(ID, MVT::i32));
-          Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
+          Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
         }
       } else {
         Result = Tmp1;  // chain
@@ -889,14 +889,15 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // We generate a shuffle of InVec and ScVec, so the shuffle mask should
         // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
         // the RHS.
-        std::vector<SDOperand> ShufOps;
+        SmallVector<SDOperand, 8> ShufOps;
         for (unsigned i = 0; i != NumElts; ++i) {
           if (i != InsertPos->getValue())
             ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
           else
             ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
         }
-        SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
+        SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
+                                         &ShufOps[0], ShufOps.size());
         
         Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
                              Tmp1, ScVec, ShufMask);
@@ -985,7 +986,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       MVT::ValueType PtrVT = TLI.getPointerTy();
       SDOperand Mask = Node->getOperand(2);
       unsigned NumElems = Mask.getNumOperands();
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand,8> Ops;
       for (unsigned i = 0; i != NumElems; ++i) {
         SDOperand Arg = Mask.getOperand(i);
         if (Arg.getOpcode() == ISD::UNDEF) {
@@ -1001,7 +1002,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
                                       DAG.getConstant(Idx - NumElems, PtrVT)));
         }
       }
-      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
       break;
     }
     case TargetLowering::Promote: {
@@ -2149,7 +2150,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       assert(MVT::isVector(Node->getValueType(0)) &&
              "Cannot expand this binary operator!");
       // Expand the operation into a bunch of nasty scalar code.
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
       MVT::ValueType PtrVT = TLI.getPointerTy();
       for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
@@ -2159,7 +2160,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
         Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
       }
-      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
+      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 
+                           &Ops[0], Ops.size());
       break;
     }
     case TargetLowering::Promote: {
@@ -3556,7 +3558,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
       MVT::getIntVectorWithNumElements(NumElems);
     SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
     std::vector<SDOperand> ZeroVec(NumElems, Zero);
-    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
+    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                                      &ZeroVec[0], ZeroVec.size());
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
     if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
@@ -3586,12 +3589,13 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
         MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
       i += NumElems;
     }
-    SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+    SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                                        &MaskVec[0], MaskVec.size());
 
     // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
     if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
         isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
             E = Values.end(); I != E; ++I) {
         SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
@@ -3601,7 +3605,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
       Ops.push_back(ShuffleMask);
 
       // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
-      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
+      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 
+                         &Ops[0], Ops.size());
     }
   }
   
@@ -3613,7 +3618,7 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   SDOperand FIPtr = CreateStackTemporary(VT);
   
   // Emit a store of each element to the stack slot.
-  std::vector<SDOperand> Stores;
+  SmallVector<SDOperand, 8> Stores;
   unsigned TypeByteSize = 
     MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
   unsigned VectorSize = MVT::getSizeInBits(VT)/8;
@@ -3634,7 +3639,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   
   SDOperand StoreChain;
   if (!Stores.empty())    // Not all undef elements?
-    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                             &Stores[0], Stores.size());
   else
     StoreChain = DAG.getEntryNode();
   
@@ -3658,12 +3664,9 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
   SDOperand LHSL, LHSH;
   ExpandOp(Op, LHSL, LHSH);
 
-  std::vector<SDOperand> Ops;
-  Ops.push_back(LHSL);
-  Ops.push_back(LHSH);
-  Ops.push_back(Amt);
+  SDOperand Ops[] = { LHSL, LHSH, Amt };
   std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
-  Lo = DAG.getNode(NodeOp, VTs, Ops);
+  Lo = DAG.getNode(NodeOp, VTs, Ops, 3);
   Hi = Lo.getValue(1);
 }
 
@@ -4634,21 +4637,21 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     ExpandOp(Node->getOperand(0), LHSL, LHSH);
     ExpandOp(Node->getOperand(1), RHSL, RHSH);
     std::vector<MVT::ValueType> VTs;
-    std::vector<SDOperand> LoOps, HiOps;
+    SDOperand LoOps[2], HiOps[2];
     VTs.push_back(LHSL.getValueType());
     VTs.push_back(MVT::Flag);
-    LoOps.push_back(LHSL);
-    LoOps.push_back(RHSL);
-    HiOps.push_back(LHSH);
-    HiOps.push_back(RHSH);
+    LoOps[0] = LHSL;
+    LoOps[1] = RHSL;
+    HiOps[0] = LHSH;
+    HiOps[1] = RHSH;
     if (Node->getOpcode() == ISD::ADD) {
-      Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
-      HiOps.push_back(Lo.getValue(1));
-      Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
+      Lo = DAG.getNode(ISD::ADDC, VTs, LoOps, 2);
+      HiOps[2] = Lo.getValue(1);
+      Hi = DAG.getNode(ISD::ADDE, VTs, HiOps, 3);
     } else {
-      Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
-      HiOps.push_back(Lo.getValue(1));
-      Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
+      Lo = DAG.getNode(ISD::SUBC, VTs, LoOps, 2);
+      HiOps[2] = Lo.getValue(1);
+      Hi = DAG.getNode(ISD::SUBE, VTs, HiOps, 3);
     }
     break;
   }
@@ -4732,15 +4735,17 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
 #endif
     assert(0 && "Unhandled operation in SplitVectorOp!");
   case ISD::VBUILD_VECTOR: {
-    std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
+    SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 
+                                    Node->op_begin()+NewNumElts);
     LoOps.push_back(NewNumEltsNode);
     LoOps.push_back(TypeNode);
-    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
+    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
 
-    std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
+    SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 
+                                    Node->op_end()-2);
     HiOps.push_back(NewNumEltsNode);
     HiOps.push_back(TypeNode);
-    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
+    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
     break;
   }
   case ISD::VADD:
@@ -4891,8 +4896,8 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
       if (AllUndef) {
         Result = DAG.getNode(ISD::UNDEF, NewVT);
       } else {
-        std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
-        Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
+        Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
+                             Node->getNumOperands()-2);
       }
     }
     break;
@@ -4920,7 +4925,9 @@ SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
       std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
                                          Node->getOperand(2).Val->op_end()-2);
       MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
-      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
+      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
+                                 Node->getOperand(2).Val->op_begin(),
+                                 Node->getOperand(2).Val->getNumOperands()-2);
       
       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
                            PackVectorOp(Node->getOperand(0), NewVT),
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 154a6ca107a..c6e20574456 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1539,16 +1539,11 @@ SDOperand SelectionDAG::getVecLoad(unsigned Count, MVT::ValueType EVT,
 SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT,
                                    SDOperand Chain, SDOperand Ptr, SDOperand SV,
                                    MVT::ValueType EVT) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(4);
-  Ops.push_back(Chain);
-  Ops.push_back(Ptr);
-  Ops.push_back(SV);
-  Ops.push_back(getValueType(EVT));
+  SDOperand Ops[] = { Chain, Ptr, SV, getValueType(EVT) };
   std::vector<MVT::ValueType> VTs;
   VTs.reserve(2);
   VTs.push_back(VT); VTs.push_back(MVT::Other);  // Add token chain.
-  return getNode(Opcode, VTs, Ops);
+  return getNode(Opcode, VTs, Ops, 4);
 }
 
 SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
@@ -1565,15 +1560,11 @@ SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
 SDOperand SelectionDAG::getVAArg(MVT::ValueType VT,
                                  SDOperand Chain, SDOperand Ptr,
                                  SDOperand SV) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(3);
-  Ops.push_back(Chain);
-  Ops.push_back(Ptr);
-  Ops.push_back(SV);
+  SDOperand Ops[] = { Chain, Ptr, SV };
   std::vector<MVT::ValueType> VTs;
   VTs.reserve(2);
   VTs.push_back(VT); VTs.push_back(MVT::Other);  // Add token chain.
-  return getNode(ISD::VAARG, VTs, Ops);
+  return getNode(ISD::VAARG, VTs, Ops, 3);
 }
 
 SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
@@ -1719,17 +1710,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode,
   return SDOperand(N, 0);
 }
 
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
-                                std::vector<SDOperand> &Ops) {
-  return getNode(Opcode, VT, &Ops[0], Ops.size());
-}
-
-SDOperand SelectionDAG::getNode(unsigned Opcode, 
-                                std::vector<MVT::ValueType> &ResultTys,
-                                std::vector<SDOperand> &Ops) {
-  return getNode(Opcode, ResultTys, &Ops[0], Ops.size());
-}
-
 
 MVT::ValueType *SelectionDAG::getNodeValueTypes(MVT::ValueType VT) {
   return SDNode::getValueTypeList(VT);
@@ -2233,59 +2213,33 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5,
                                     SDOperand Op6) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(6);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 6).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5, SDOperand Op6,
                                     SDOperand Op7) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(7);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  Ops.push_back(Op7);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 7).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
                                     SDOperand Op1, SDOperand Op2, SDOperand Op3,
                                     SDOperand Op4, SDOperand Op5, SDOperand Op6,
                                     SDOperand Op7, SDOperand Op8) {
-  std::vector<SDOperand> Ops;
-  Ops.reserve(8);
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  Ops.push_back(Op7);
-  Ops.push_back(Op8);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 8).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
-                                    std::vector<SDOperand> &Ops) {
-  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+                                    const SDOperand *Ops, unsigned NumOps) {
+  return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, NumOps).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1) {
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, &Op1, 1).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2293,10 +2247,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 2).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2304,11 +2256,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 3).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2317,12 +2266,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 4).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2331,13 +2276,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 5).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2346,14 +2286,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 6).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, SDOperand Op1,
@@ -2363,15 +2297,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6); 
-  Ops.push_back(Op7);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 7).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2380,10 +2307,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
   ResultTys.push_back(VT3);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 2).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2394,13 +2319,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
   ResultTys.push_back(VT3);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 5).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2411,14 +2331,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
   ResultTys.push_back(VT3);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 6).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
                                     MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2429,23 +2343,16 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
   ResultTys.push_back(VT3);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  Ops.push_back(Op5);
-  Ops.push_back(Op6);
-  Ops.push_back(Op7);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 7).Val;
 }
 SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1, 
                                     MVT::ValueType VT2,
-                                    std::vector<SDOperand> &Ops) {
+                                    const SDOperand *Ops, unsigned NumOps) {
   std::vector<MVT::ValueType> ResultTys;
   ResultTys.push_back(VT1);
   ResultTys.push_back(VT2);
-  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+  return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, NumOps).Val;
 }
 
 /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 1af367a7e7f..b0bda0f8c23 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -437,7 +437,8 @@ public:
     }
 
     // Otherwise, we have to make a token factor node.
-    SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
+    SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                                 &PendingLoads[0], PendingLoads.size());
     PendingLoads.clear();
     DAG.setRoot(Root);
     return Root;
@@ -598,13 +599,14 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
       unsigned NumElements = PTy->getNumElements();
       MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
 
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
       
       // Create a VConstant node with generic Vector type.
       Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
       Ops.push_back(DAG.getValueType(PVT));
-      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+                             &Ops[0], Ops.size());
     } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
       return N = DAG.getConstantFP(CFP->getValue(), VT);
     } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
@@ -614,7 +616,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
       // Now that we know the number and type of the elements, push a
       // Constant or ConstantFP node onto the ops list for each element of
       // the packed constant.
-      std::vector<SDOperand> Ops;
+      SmallVector<SDOperand, 8> Ops;
       if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
         for (unsigned i = 0; i != NumElements; ++i)
           Ops.push_back(getValue(CP->getOperand(i)));
@@ -631,7 +633,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
       // Create a VBUILD_VECTOR node with generic Vector type.
       Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
       Ops.push_back(DAG.getValueType(PVT));
-      return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+      return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
     } else {
       // Canonicalize all constant ints to be unsigned.
       return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
@@ -676,7 +678,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
                                              PTyLegalElementVT);
 
     // Build a VBUILD_VECTOR with the input registers.
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     if (PTyElementVT == PTyLegalElementVT) {
       // If the value types are legal, just VBUILD the CopyFromReg nodes.
       for (unsigned i = 0; i != NE; ++i)
@@ -707,7 +709,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
     
     Ops.push_back(DAG.getConstant(NE, MVT::i32));
     Ops.push_back(DAG.getValueType(PTyLegalElementVT));
-    N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+    N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
     
     // Finally, use a VBIT_CONVERT to make this available as the appropriate
     // vector type.
@@ -726,7 +728,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
     DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
     return;
   }
-  std::vector<SDOperand> NewValues;
+  SmallVector<SDOperand, 8> NewValues;
   NewValues.push_back(getRoot());
   for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
     SDOperand RetOp = getValue(I.getOperand(i));
@@ -753,7 +755,8 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
     NewValues.push_back(RetOp);
     NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
   }
-  DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
+  DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
+                          &NewValues[0], NewValues.size()));
 }
 
 void SelectionDAGLowering::visitBr(BranchInst &I) {
@@ -1346,11 +1349,8 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
   std::vector<MVT::ValueType> VTs;
   VTs.push_back(AllocSize.getValueType());
   VTs.push_back(MVT::Other);
-  std::vector<SDOperand> Ops;
-  Ops.push_back(getRoot());
-  Ops.push_back(AllocSize);
-  Ops.push_back(getIntPtrConstant(Align));
-  SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
+  SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
+  SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops, 3);
   DAG.setRoot(setValue(&I, DSA).getValue(1));
 
   // Inform the Frame Information that we have just allocated a variable-sized
@@ -1427,7 +1427,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
   bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
   
   // Build the operand list.
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   if (HasChain) {  // If this intrinsic has side-effects, chainify it.
     if (OnlyLoad) {
       // We don't need to serialize loads against other loads.
@@ -1479,11 +1479,11 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
   // Create the node.
   SDOperand Result;
   if (!HasChain)
-    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
+    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, &Ops[0], Ops.size());
   else if (I.getType() != Type::VoidTy)
-    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
+    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, &Ops[0], Ops.size());
   else
-    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
+    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, &Ops[0], Ops.size());
 
   if (HasChain) {
     SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
@@ -1541,20 +1541,20 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
     if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
-      std::vector<SDOperand> Ops;
+      SDOperand Ops[5];
 
-      Ops.push_back(getRoot());
-      Ops.push_back(getValue(SPI.getLineValue()));
-      Ops.push_back(getValue(SPI.getColumnValue()));
+      Ops[0] = getRoot();
+      Ops[1] = getValue(SPI.getLineValue());
+      Ops[2] = getValue(SPI.getColumnValue());
 
       DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
       assert(DD && "Not a debug information descriptor");
       CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
       
-      Ops.push_back(DAG.getString(CompileUnit->getFileName()));
-      Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
+      Ops[3] = DAG.getString(CompileUnit->getFileName());
+      Ops[4] = DAG.getString(CompileUnit->getDirectory());
       
-      DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
+      DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
     }
 
     return 0;
@@ -1563,14 +1563,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
     if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
-      std::vector<SDOperand> Ops;
-
       unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
-      
-      Ops.push_back(getRoot());
-      Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
-      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
+                              DAG.getConstant(LabelID, MVT::i32)));
     }
 
     return 0;
@@ -1579,14 +1574,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
     if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
-      std::vector<SDOperand> Ops;
-
       unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
-      
-      Ops.push_back(getRoot());
-      Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
-      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+                              getRoot(), DAG.getConstant(LabelID, MVT::i32)));
     }
 
     return 0;
@@ -1596,14 +1586,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
     if (DebugInfo && FSI.getSubprogram() &&
         DebugInfo->Verify(FSI.getSubprogram())) {
-      std::vector<SDOperand> Ops;
-
       unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
-      
-      Ops.push_back(getRoot());
-      Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
-      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+      DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+                  getRoot(), DAG.getConstant(LabelID, MVT::i32)));
     }
 
     return 0;
@@ -1612,12 +1597,9 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
     DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
     if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
-      std::vector<SDOperand> Ops;
-
       SDOperand AddressOp  = getValue(DI.getAddress());
-      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
+      if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
         DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
-      }
     }
 
     return 0;
@@ -1644,9 +1626,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(MVT::i64);
     VTs.push_back(MVT::Other);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(getRoot());
-    SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
+    SDOperand Op = getRoot();
+    SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
     return 0;
@@ -1686,9 +1667,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     std::vector<MVT::ValueType> VTs;
     VTs.push_back(TLI.getPointerTy());
     VTs.push_back(MVT::Other);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(getRoot());
-    SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
+    SDOperand Op = getRoot();
+    SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, &Op, 1);
     setValue(&I, Tmp);
     DAG.setRoot(Tmp.getValue(1));
     return 0;
@@ -2279,7 +2259,8 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
   std::vector<MVT::ValueType> VTs;
   VTs.push_back(MVT::Other);
   VTs.push_back(MVT::Flag);
-  Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
+  Chain = DAG.getNode(ISD::INLINEASM, VTs,
+                      &AsmNodeOperands[0], AsmNodeOperands.size());
   Flag = Chain.getValue(1);
 
   // If this asm returns a register value, copy the result from that register
@@ -2299,14 +2280,15 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
   }
   
   // Emit the non-flagged stores from the physregs.
-  std::vector<SDOperand> OutChains;
+  SmallVector<SDOperand, 8> OutChains;
   for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
     OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 
                                     StoresToEmit[i].first,
                                     getValue(StoresToEmit[i].second),
                                     DAG.getSrcValue(StoresToEmit[i].second)));
   if (!OutChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
+    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                        &OutChains[0], OutChains.size());
   DAG.setRoot(Chain);
 }
 
@@ -2446,7 +2428,8 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   RetVals.push_back(MVT::Other);
   
   // Create the node.
-  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
+  SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals,
+                               &Ops[0], Ops.size()).Val;
   
   DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
 
@@ -2653,7 +2636,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
   RetTys.push_back(MVT::Other);  // Always has a chain.
   
   // Finally, create the CALL node.
-  SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
+  SDOperand Res = DAG.getNode(ISD::CALL, RetTys, &Ops[0], Ops.size());
   
   // This returns a pair of operands.  The first element is the
   // return value for the function (if RetTy is not VoidTy).  The second
@@ -2862,7 +2845,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
 
     // Expand memset / memcpy to a series of load / store ops
     // if the size operand falls below a certain threshold.
-    std::vector<SDOperand> OutChains;
+    SmallVector<SDOperand, 8> OutChains;
     switch (Op) {
     default: break;  // Do nothing for now.
     case ISD::MEMSET: {
@@ -2944,18 +2927,13 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
     }
 
     if (!OutChains.empty()) {
-      DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+      DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+                  &OutChains[0], OutChains.size()));
       return;
     }
   }
 
-  std::vector<SDOperand> Ops;
-  Ops.push_back(getRoot());
-  Ops.push_back(Op1);
-  Ops.push_back(Op2);
-  Ops.push_back(Op3);
-  Ops.push_back(Op4);
-  DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
+  DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
 }
 
 //===----------------------------------------------------------------------===//
@@ -3318,7 +3296,7 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
     // Loop over all of the elements of the resultant vector,
     // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
     // copying them into output registers.
-    std::vector<SDOperand> OutChains;
+    SmallVector<SDOperand, 8> OutChains;
     SDOperand Root = SDL.getRoot();
     for (unsigned i = 0; i != NE; ++i) {
       SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
@@ -3344,7 +3322,8 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
         OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
       }
     }
-    return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
+    return DAG.getNode(ISD::TokenFactor, MVT::Other,
+                       &OutChains[0], OutChains.size());
   } else if (SrcVT < DestVT) {
     // The src value is promoted to the register.
     if (MVT::isFloatingPoint(SrcVT))
@@ -3500,7 +3479,8 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
       if (i == e)
         UnorderedChains.push_back(Root);
     }
-    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
+    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+                            &UnorderedChains[0], UnorderedChains.size()));
   }
 
   // Lower the terminator after the copies are emitted.
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 4346c5e21d4..106243a68f9 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1152,7 +1152,7 @@ void PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) {
   bool hasFlag =
     N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
 
-  std::vector<SDOperand> Ops;
+  SmallVector<SDOperand, 8> Ops;
   // Push varargs arguments, including optional flag.
   for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
     AddToQueue(Chain, N.getOperand(i));
@@ -1167,7 +1167,8 @@ void PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand &Result, SDOperand N) {
     Ops.push_back(Chain);
   }
   
-  ResNode = CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag, Ops);
+  ResNode = CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
+                                  &Ops[0], Ops.size());
   Chain = SDOperand(ResNode, 0);
   InFlag = SDOperand(ResNode, 1);
   ReplaceUses(SDOperand(N.Val, 0), Chain);
@@ -1193,7 +1194,7 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
   if (N1.getOpcode() == ISD::Constant) {
     unsigned Tmp0C = (unsigned)cast<ConstantSDNode>(N1)->getValue();
     
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32));
 
     bool hasFlag =
@@ -1210,7 +1211,8 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
       AddToQueue(Chain, N.getOperand(N.getNumOperands()-1));
       Ops.push_back(Chain);
     }
-    ResNode = CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag, Ops);
+    ResNode = CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
+                                    &Ops[0], Ops.size());
     
     Chain = SDOperand(ResNode, 0);
     InFlag = SDOperand(ResNode, 1);
@@ -1224,7 +1226,7 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
   // Emits: (BL:void (tglobaladdr:i32):$dst)
   // Pattern complexity = 4  cost = 1
   if (N1.getOpcode() == ISD::TargetGlobalAddress) {
-    std::vector<SDOperand> Ops;
+    SmallVector<SDOperand, 8> Ops;
     Ops.push_back(N1);
     
     bool hasFlag =
@@ -1242,7 +1244,8 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
       Ops.push_back(Chain);
     }
     
-    ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag, Ops);
+    ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
+                                    &Ops[0], Ops.size());
     
     Chain = SDOperand(ResNode, 0);
     InFlag = SDOperand(ResNode, 1);
@@ -1274,7 +1277,8 @@ void PPCDAGToDAGISel::MySelect_PPCcall(SDOperand &Result, SDOperand N) {
       Ops.push_back(Chain);
     }
     
-    ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag, Ops);
+    ResNode = CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
+                                    &Ops[0], Ops.size());
 
     Chain = SDOperand(ResNode, 0);
     InFlag = SDOperand(ResNode, 1);
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a0f52f0f3ef..765982dd2dd 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -444,7 +444,8 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   }
   
   if (!OutChains.empty())
-    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+                            &OutChains[0], OutChains.size()));
   
   // Finally, inform the code generator which regs we return values in.
   switch (getValueType(F.getReturnType())) {
@@ -596,7 +597,7 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
   
   // Emit all stores, make sure the occur before any copies into physregs.
   if (!Stores.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
   
   static const unsigned ArgRegs[] = {
     SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
@@ -621,12 +622,8 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
   std::vector<MVT::ValueType> NodeTys;
   NodeTys.push_back(MVT::Other);   // Returns a chain
   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
-  std::vector<SDOperand> Ops;
-  Ops.push_back(Chain);
-  Ops.push_back(Callee);
-  if (InFlag.Val)
-    Ops.push_back(InFlag);
-  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
+  SDOperand Ops[] = { Chain, Callee, InFlag };
+  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
   InFlag = Chain.getValue(1);
   
   MVT::ValueType RetTyVT = getValueType(RetTy);
@@ -743,10 +740,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       std::vector<MVT::ValueType> VTs;
       VTs.push_back(MVT::i32);
       VTs.push_back(MVT::Flag);
-      std::vector<SDOperand> Ops;
-      Ops.push_back(LHS);
-      Ops.push_back(RHS);
-      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+      SDOperand Ops[2] = { LHS, RHS };
+      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
       if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
       Opc = SPISD::BRICC;
     } else {
@@ -774,10 +769,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       std::vector<MVT::ValueType> VTs;
       VTs.push_back(LHS.getValueType());   // subcc returns a value
       VTs.push_back(MVT::Flag);
-      std::vector<SDOperand> Ops;
-      Ops.push_back(LHS);
-      Ops.push_back(RHS);
-      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+      SDOperand Ops[2] = { LHS, RHS };
+      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
       Opc = SPISD::SELECT_ICC;
       if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
     } else {
@@ -821,11 +814,10 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       std::vector<MVT::ValueType> Tys;
       Tys.push_back(MVT::f64);
       Tys.push_back(MVT::Other);
-      std::vector<SDOperand> Ops;
       // Bit-Convert the value to f64.
-      Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
-      Ops.push_back(V.getValue(1));
-      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+      SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
+                           V.getValue(1) };
+      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
     }
   }
   case ISD::DYNAMIC_STACKALLOC: {
@@ -844,10 +836,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     std::vector<MVT::ValueType> Tys;
     Tys.push_back(MVT::i32);
     Tys.push_back(MVT::Other);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(NewVal);
-    Ops.push_back(Chain);
-    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+    SDOperand Ops[2] = { NewVal, Chain };
+    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
   }
   case ISD::RET: {
     SDOperand Copy;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index cb81f72834b..5a390356eb7 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -479,7 +479,7 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
   // Return the new list of results.
   std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
                                      Op.Val->value_end());
-  return DAG.getNode(ISD::MERGE_VALUES, RetVTs, ArgValues);
+  return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
 }
 
 
@@ -596,7 +596,8 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
   }
 
   if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
+    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                        &MemOpChains[0], MemOpChains.size());
 
   // Build a sequence of copy-to-reg nodes chained together with token chain
   // and flag operands which copy the outgoing args into registers.
@@ -631,7 +632,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
     Ops.push_back(InFlag);
 
   Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
-                      NodeTys, Ops);
+                      NodeTys, &Ops[0], Ops.size());
   InFlag = Chain.getValue(1);
 
   // Create the CALLSEQ_END node.
@@ -651,7 +652,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
   Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
   Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
   Ops.push_back(InFlag);
-  Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
+  Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
   if (RetVT != MVT::Other)
     InFlag = Chain.getValue(1);
   
@@ -703,7 +704,8 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
     std::vector<SDOperand> Ops;
     Ops.push_back(Chain);
     Ops.push_back(InFlag);
-    SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
+    SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, 
+                                   &Ops[0], Ops.size());
     Chain  = RetVal.getValue(1);
     InFlag = RetVal.getValue(2);
     if (X86ScalarSSE) {
@@ -721,7 +723,7 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(StackSlot);
       Ops.push_back(DAG.getValueType(RetVT));
       Ops.push_back(InFlag);
-      Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
+      Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
       RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
                            DAG.getSrcValue(NULL));
       Chain = RetVal.getValue(1);
@@ -744,7 +746,8 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
   // Otherwise, merge everything together with a MERGE_VALUES node.
   NodeTys.push_back(MVT::Other);
   ResultVals.push_back(Chain);
-  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
+  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
+                              &ResultVals[0], ResultVals.size());
   return Res.getValue(Op.ResNo);
 }
 
@@ -980,10 +983,10 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
   // Return the new list of results.
   std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
                                      Op.Val->value_end());
-  return DAG.getNode(ISD::MERGE_VALUES, RetVTs, ArgValues);
+  return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
 }
 
-SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG) {
+SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG){
   SDOperand Chain     = Op.getOperand(0);
   unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   bool isVarArg       = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
@@ -1117,7 +1120,8 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
   }
 
   if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
+    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+                        &MemOpChains[0], MemOpChains.size());
 
   // Build a sequence of copy-to-reg nodes chained together with token chain
   // and flag operands which copy the outgoing args into registers.
@@ -1153,7 +1157,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
 
   // FIXME: Do not generate X86ISD::TAILCALL for now.
   Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
-                      NodeTys, Ops);
+                      NodeTys, &Ops[0], Ops.size());
   InFlag = Chain.getValue(1);
 
   NodeTys.clear();
@@ -1165,7 +1169,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
   Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
   Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
   Ops.push_back(InFlag);
-  Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
+  Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
   if (RetVT != MVT::Other)
     InFlag = Chain.getValue(1);
   
@@ -1217,7 +1221,8 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
     std::vector<SDOperand> Ops;
     Ops.push_back(Chain);
     Ops.push_back(InFlag);
-    SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
+    SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
+                                   &Ops[0], Ops.size());
     Chain  = RetVal.getValue(1);
     InFlag = RetVal.getValue(2);
     if (X86ScalarSSE) {
@@ -1235,7 +1240,7 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
       Ops.push_back(StackSlot);
       Ops.push_back(DAG.getValueType(RetVT));
       Ops.push_back(InFlag);
-      Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
+      Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
       RetVal = DAG.getLoad(RetVT, Chain, StackSlot,
                            DAG.getSrcValue(NULL));
       Chain = RetVal.getValue(1);
@@ -1259,7 +1264,8 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG)
   // Otherwise, merge everything together with a MERGE_VALUES node.
   NodeTys.push_back(MVT::Other);
   ResultVals.push_back(Chain);
-  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
+  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
+                              &ResultVals[0], ResultVals.size());
   return Res.getValue(Op.ResNo);
 }
 
@@ -1963,7 +1969,7 @@ static SDOperand CommuteVectorShuffle(SDOperand Op, SelectionDAG &DAG) {
       MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
   }
 
-  Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+  Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
   return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
 }
 
@@ -2049,7 +2055,8 @@ static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
   }
 
   if (Changed)
-    Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
+    Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
+                       &MaskVec[0], MaskVec.size());
   return Mask;
 }
 
@@ -2063,7 +2070,7 @@ static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
   MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
   for (unsigned i = 1; i != NumElems; ++i)
     MaskVec.push_back(DAG.getConstant(i, BaseVT));
-  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
 }
 
 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
@@ -2076,7 +2083,7 @@ static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
     MaskVec.push_back(DAG.getConstant(i,            BaseVT));
     MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
   }
-  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
 }
 
 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
@@ -2090,7 +2097,7 @@ static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
     MaskVec.push_back(DAG.getConstant(i + Half,            BaseVT));
     MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
   }
-  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+  return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
 }
 
 /// getZeroVector - Returns a vector of specified type with all zero elements.
@@ -2102,7 +2109,7 @@ static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
   bool isFP = MVT::isFloatingPoint(EVT);
   SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
   std::vector<SDOperand> ZeroVec(NumElems, Zero);
-  return DAG.getNode(ISD::BUILD_VECTOR, VT, ZeroVec);
+  return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
 }
 
 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
@@ -2146,7 +2153,8 @@ static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
   SDOperand Zero = DAG.getConstant(0, EVT);
   std::vector<SDOperand> MaskVec(NumElems, Zero);
   MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
-  SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+  SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                               &MaskVec[0], MaskVec.size());
   return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
 }
 
@@ -2281,7 +2289,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
       std::vector<SDOperand> MaskVec;
       for (unsigned i = 0; i < NumElems; i++)
         MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
-      SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+      SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+                                   &MaskVec[0], MaskVec.size());
       return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
                          DAG.getNode(ISD::UNDEF, VT), Mask);
     }
@@ -2832,7 +2841,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
+      Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
       InFlag = Hi.getValue(1);
 
       Ops.clear();
@@ -2840,13 +2849,13 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
+      Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
     } else {
       Ops.push_back(Tmp2);
       Ops.push_back(Tmp3);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
+      Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
       InFlag = Lo.getValue(1);
 
       Ops.clear();
@@ -2854,7 +2863,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
       Ops.push_back(Tmp1);
       Ops.push_back(CC);
       Ops.push_back(InFlag);
-      Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
+      Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
     }
 
     Tys.clear();
@@ -2863,7 +2872,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
     Ops.clear();
     Ops.push_back(Lo);
     Ops.push_back(Hi);
-    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+    return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
 }
 
 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
@@ -2891,7 +2900,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   Ops.push_back(StackSlot);
   Ops.push_back(DAG.getValueType(SrcVT));
   Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
-                       Tys, Ops);
+                       Tys, &Ops[0], Ops.size());
 
   if (X86ScalarSSE) {
     Chain = Result.getValue(1);
@@ -2911,7 +2920,7 @@ SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
     Ops.push_back(StackSlot);
     Ops.push_back(DAG.getValueType(Op.getValueType()));
     Ops.push_back(InFlag);
-    Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
+    Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
     Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
                          DAG.getSrcValue(NULL));
   }
@@ -2950,7 +2959,7 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
     Ops.push_back(Chain);
     Ops.push_back(StackSlot);
     Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
-    Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
+    Value = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
     Chain = Value.getValue(1);
     SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
     StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
@@ -3040,7 +3049,7 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
         Tys.push_back(MVT::Flag);
         Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
         Ops.push_back(Cond);
-        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
         SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                      DAG.getConstant(X86ISD::COND_E, MVT::i8),
                                      Tmp1.getValue(1));
@@ -3051,7 +3060,7 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
         Tys.push_back(MVT::Flag);
         Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
         Ops.push_back(Cond);
-        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+        SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
         SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
                                      DAG.getConstant(X86ISD::COND_NE, MVT::i8),
                                      Tmp1.getValue(1));
@@ -3087,7 +3096,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
         std::vector<SDOperand> Ops;
         for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
           Ops.push_back(Op0.getOperand(i));
-        Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
+        Op0 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
       }
 
       CC   = Op0.getOperand(0);
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index f03c7c3b0da..8a887017c1e 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -2683,7 +2683,7 @@ public:
         }
 
         if (HasVarOps)
-          Code += ", Ops";
+          Code += ", &Ops[0], Ops.size()";
         else if (NodeHasOptInFlag)
           Code = "HasInFlag ? " + Code + ", InFlag) : " + Code;
 
@@ -3420,7 +3420,8 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
      << "  std::vector<MVT::ValueType> VTs;\n"
      << "  VTs.push_back(MVT::Other);\n"
      << "  VTs.push_back(MVT::Flag);\n"
-     << "  SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, Ops);\n"
+     << "  SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
+                 "Ops.size());\n"
      << "  ReplaceUses(SDOperand(N.Val, 0), New);\n"
      << "  ReplaceUses(SDOperand(N.Val, 1), SDOperand(New.Val, 1));\n"
      << "  Result = New.getValue(N.ResNo);\n"