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https://github.com/c64scene-ar/llvm-6502.git
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Implement ISD::VAARG lowering on PPC32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Divacky
parent
4f91054fe4
commit
bdb226ec83
@ -216,9 +216,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// VAARG is custom lowered with the 32-bit SVR4 ABI.
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if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
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&& !TM.getSubtarget<PPCSubtarget>().isPPC64())
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&& !TM.getSubtarget<PPCSubtarget>().isPPC64()) {
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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else
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setOperationAction(ISD::VAARG, MVT::i64, Custom);
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} else
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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// Use the default implementation.
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@ -1262,9 +1263,110 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) const {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getValueType(0);
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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SDValue InChain = Node->getOperand(0);
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SDValue VAListPtr = Node->getOperand(1);
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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DebugLoc dl = Node->getDebugLoc();
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llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
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return SDValue(); // Not reached
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assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
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// gpr_index
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SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
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VAListPtr, MachinePointerInfo(SV), MVT::i8,
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false, false, 0);
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InChain = GprIndex.getValue(1);
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if (VT == MVT::i64) {
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// Check if GprIndex is even
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SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
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DAG.getConstant(1, MVT::i32));
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SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
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DAG.getConstant(0, MVT::i32), ISD::SETNE);
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SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
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DAG.getConstant(1, MVT::i32));
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// Align GprIndex to be even if it isn't
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GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
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GprIndex);
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}
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// fpr index is 1 byte after gpr
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SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
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DAG.getConstant(1, MVT::i32));
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// fpr
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SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
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FprPtr, MachinePointerInfo(SV), MVT::i8,
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false, false, 0);
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InChain = FprIndex.getValue(1);
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SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
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DAG.getConstant(8, MVT::i32));
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SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
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DAG.getConstant(4, MVT::i32));
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// areas
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SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
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MachinePointerInfo(), false, false, 0);
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InChain = OverflowArea.getValue(1);
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SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
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MachinePointerInfo(), false, false, 0);
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InChain = RegSaveArea.getValue(1);
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// select overflow_area if index > 8
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SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
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DAG.getConstant(8, MVT::i32), ISD::SETLT);
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SDValue Area = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, RegSaveArea,
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OverflowArea);
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// adjustment constant gpr_index * 4/8
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SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
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VT.isInteger() ? GprIndex : FprIndex,
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DAG.getConstant(VT.isInteger() ? 4 : 8,
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MVT::i32));
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// OurReg = RegSaveArea + RegConstant
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SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
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RegConstant);
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// Floating types are 32 bytes into RegSaveArea
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if (VT.isFloatingPoint())
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OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
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DAG.getConstant(32, MVT::i32));
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// increase {f,g}pr_index by 1 (or 2 if VT is i64)
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SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
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VT.isInteger() ? GprIndex : FprIndex,
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DAG.getConstant(VT == MVT::i64 ? 2 : 1,
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MVT::i32));
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InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
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VT.isInteger() ? VAListPtr : FprPtr,
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MachinePointerInfo(SV),
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MVT::i8, false, false, 0);
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// determine if we should load from reg_save_area or overflow_area
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SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
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// increase overflow_area by 4/8 if gpr/fpr > 8
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SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
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DAG.getConstant(VT.isInteger() ? 4 : 8,
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MVT::i32));
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OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
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OverflowAreaPlusN);
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InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
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OverflowAreaPtr,
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MachinePointerInfo(),
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MVT::i32, false, false, 0);
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return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0);
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}
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SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
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@ -4429,11 +4531,27 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const {
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const TargetMachine &TM = getTargetMachine();
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DebugLoc dl = N->getDebugLoc();
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switch (N->getOpcode()) {
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default:
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assert(false && "Do not know how to custom type legalize this operation!");
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return;
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case ISD::VAARG: {
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if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
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|| TM.getSubtarget<PPCSubtarget>().isPPC64())
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return;
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EVT VT = N->getValueType(0);
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if (VT == MVT::i64) {
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SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
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Results.push_back(NewNode);
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Results.push_back(NewNode.getValue(1));
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}
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return;
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}
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case ISD::FP_ROUND_INREG: {
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assert(N->getValueType(0) == MVT::ppcf128);
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assert(N->getOperand(0).getValueType() == MVT::ppcf128);
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167
test/CodeGen/PowerPC/ppc32-vaarg.ll
Normal file
167
test/CodeGen/PowerPC/ppc32-vaarg.ll
Normal file
@ -0,0 +1,167 @@
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; RUN: llc -O0 < %s | FileCheck %s
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;ModuleID = 'test.c'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
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target triple = "powerpc-unknown-freebsd9.0"
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%struct.__va_list_tag = type { i8, i8, i16, i8*, i8* }
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@var1 = common global i64 0, align 8
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@var2 = common global double 0.0, align 8
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@var3 = common global i32 0, align 4
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define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
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entry:
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%x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
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; CHECK: lbz 4, 0(3)
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; CHECK-NEXT: lwz 5, 4(3)
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; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
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; CHECK-NEXT: cmplwi 0, 6, 0
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; CHECK-NEXT: addi 6, 4, 1
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; CHECK-NEXT: stw 3, -4(1)
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; CHECK-NEXT: stw 6, -8(1)
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; CHECK-NEXT: stw 4, -12(1)
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; CHECK-NEXT: stw 5, -16(1)
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; CHECK-NEXT: bne 0, .LBB0_2
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; CHECK-NEXT: # BB#1: # %entry
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; CHECK-NEXT: lwz 3, -12(1)
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; CHECK-NEXT: stw 3, -8(1)
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: lwz 3, -8(1)
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; CHECK-NEXT: lwz 4, -4(1)
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; CHECK-NEXT: lwz 5, 8(4)
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; CHECK-NEXT: slwi 6, 3, 2
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; CHECK-NEXT: addi 7, 3, 2
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: lwz 3, -16(1)
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; CHECK-NEXT: addi 8, 3, 4
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; CHECK-NEXT: add 5, 5, 6
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -20(1)
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; CHECK-NEXT: stw 5, -24(1)
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; CHECK-NEXT: stw 3, -28(1)
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; CHECK-NEXT: stw 7, -32(1)
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; CHECK-NEXT: stw 8, -36(1)
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; CHECK-NEXT: blt 0, .LBB0_4
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; CHECK-NEXT: # BB#3: # %entry
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; CHECK-NEXT: lwz 3, -36(1)
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; CHECK-NEXT: stw 3, -28(1)
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; CHECK-NEXT: .LBB0_4: # %entry
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; CHECK-NEXT: lwz 3, -28(1)
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; CHECK-NEXT: lwz 4, -32(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 0(5)
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; CHECK-NEXT: lwz 4, -24(1)
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; CHECK-NEXT: lwz 0, -20(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 3, -40(1)
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; CHECK-NEXT: stw 4, -44(1)
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; CHECK-NEXT: blt 0, .LBB0_6
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; CHECK-NEXT: # BB#5: # %entry
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; CHECK-NEXT: lwz 3, -16(1)
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; CHECK-NEXT: stw 3, -44(1)
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; CHECK-NEXT: .LBB0_6: # %entry
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; CHECK-NEXT: lwz 3, -44(1)
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; CHECK-NEXT: lwz 4, -40(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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store i64 %x, i64* @var1, align 8
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; CHECK-NEXT: lis 4, var1@ha
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; CHECK-NEXT: lwz 6, 4(3)
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: la 7, var1@l(4)
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; CHECK-NEXT: stw 3, var1@l(4)
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; CHECK-NEXT: stw 6, 4(7)
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%y = va_arg %struct.__va_list_tag* %ap, double; From f1
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; CHECK-NEXT: lbz 3, 1(5)
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; CHECK-NEXT: lwz 4, 4(5)
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; CHECK-NEXT: lwz 6, 8(5)
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; CHECK-NEXT: slwi 7, 3, 3
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; CHECK-NEXT: add 6, 6, 7
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; CHECK-NEXT: addi 7, 3, 1
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 3, 4, 8
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; CHECK-NEXT: addi 6, 6, 32
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; CHECK-NEXT: mr 8, 4
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -48(1)
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; CHECK-NEXT: stw 4, -52(1)
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; CHECK-NEXT: stw 6, -56(1)
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; CHECK-NEXT: stw 7, -60(1)
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; CHECK-NEXT: stw 3, -64(1)
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; CHECK-NEXT: stw 8, -68(1)
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; CHECK-NEXT: blt 0, .LBB0_8
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; CHECK-NEXT: # BB#7: # %entry
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; CHECK-NEXT: lwz 3, -64(1)
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; CHECK-NEXT: stw 3, -68(1)
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; CHECK-NEXT: .LBB0_8: # %entry
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; CHECK-NEXT: lwz 3, -68(1)
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; CHECK-NEXT: lwz 4, -60(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 1(5)
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; CHECK-NEXT: lwz 4, -56(1)
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; CHECK-NEXT: lwz 0, -48(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -72(1)
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; CHECK-NEXT: stw 3, -76(1)
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; CHECK-NEXT: blt 0, .LBB0_10
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; CHECK-NEXT: # BB#9: # %entry
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; CHECK-NEXT: lwz 3, -52(1)
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; CHECK-NEXT: stw 3, -72(1)
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; CHECK-NEXT: .LBB0_10: # %entry
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; CHECK-NEXT: lwz 3, -72(1)
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; CHECK-NEXT: lwz 4, -76(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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; CHECK-NEXT: lfd 0, 0(3)
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store double %y, double* @var2, align 8
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; CHECK-NEXT: lis 3, var2@ha
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; CHECK-NEXT: stfd 0, var2@l(3)
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%z = va_arg %struct.__va_list_tag* %ap, i32; From r7
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; CHECK-NEXT: lbz 3, 0(5)
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; CHECK-NEXT: lwz 4, 4(5)
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; CHECK-NEXT: lwz 6, 8(5)
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; CHECK-NEXT: slwi 7, 3, 2
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; CHECK-NEXT: addi 8, 3, 1
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 3, 4, 4
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; CHECK-NEXT: add 6, 6, 7
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; CHECK-NEXT: mr 7, 4
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; CHECK-NEXT: stw 6, -80(1)
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; CHECK-NEXT: stw 8, -84(1)
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; CHECK-NEXT: stw 3, -88(1)
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; CHECK-NEXT: stw 4, -92(1)
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; CHECK-NEXT: stw 7, -96(1)
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -100(1)
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; CHECK-NEXT: blt 0, .LBB0_12
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; CHECK-NEXT: # BB#11: # %entry
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; CHECK-NEXT: lwz 3, -88(1)
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; CHECK-NEXT: stw 3, -96(1)
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; CHECK-NEXT: .LBB0_12: # %entry
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; CHECK-NEXT: lwz 3, -96(1)
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; CHECK-NEXT: lwz 4, -84(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 0(5)
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; CHECK-NEXT: lwz 4, -80(1)
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; CHECK-NEXT: lwz 0, -100(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -104(1)
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; CHECK-NEXT: stw 3, -108(1)
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; CHECK-NEXT: blt 0, .LBB0_14
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; CHECK-NEXT: # BB#13: # %entry
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; CHECK-NEXT: lwz 3, -92(1)
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; CHECK-NEXT: stw 3, -104(1)
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; CHECK-NEXT: .LBB0_14: # %entry
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; CHECK-NEXT: lwz 3, -104(1)
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; CHECK-NEXT: lwz 4, -108(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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; CHECK-NEXT: lwz 3, 0(3)
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store i32 %z, i32* @var3, align 4
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; CHECK-NEXT: lis 4, var3@ha
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; CHECK-NEXT: stw 3, var3@l(4)
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ret void
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; CHECK-NEXT: stw 5, -112(1)
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; CHECK-NEXT: blr
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}
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