From bdce3726e2131f053d05f07ff135684ad6f11d80 Mon Sep 17 00:00:00 2001
From: Stuart Hastings <stuart@apple.com>
Date: Wed, 1 Jun 2011 14:04:17 +0000
Subject: [PATCH] Turn on FGETSIGN for x86.  Followup to 132388.
 rdar://problem/5660695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132396 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a9ac786dc6a..6739f1a8be2 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1754,27 +1754,23 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
     break;
   }
   case ISD::BITCAST:
-#if 0
     // If this is an FP->Int bitcast and if the sign bit is the only thing that
     // is demanded, turn this into a FGETSIGN.
     if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
         Op.getOperand(0).getValueType().isFloatingPoint() &&
         !Op.getOperand(0).getValueType().isVector()) {
-      // Only do this xform if FGETSIGN is valid or if before legalize.
-      if (TLO.isBeforeLegalize() ||
-          isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
+      if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) {
         // Make a FGETSIGN + SHL to move the sign bit into the appropriate
         // place.  We expect the SHL to be eliminated by other optimizations.
         SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(),
                                          Op.getOperand(0));
         unsigned ShVal = Op.getValueType().getSizeInBits()-1;
-        SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
+        SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
                                                  Op.getValueType(),
                                                  Sign, ShAmt));
       }
     }
-#endif
     break;
   case ISD::ADD:
   case ISD::MUL: