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Add DAG nodes to represent FP16 <-> FP32 intrinsics

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98500 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2010-03-14 18:42:15 +00:00
parent feacf28cf8
commit be5b032e4b
2 changed files with 14 additions and 0 deletions
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6
include/llvm/CodeGen/SelectionDAGNodes.h
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@@ -439,6 +439,12 @@ namespace ISD {
// 5) ISD::CvtCode indicating the type of conversion to do // 5) ISD::CvtCode indicating the type of conversion to do
CONVERT_RNDSAT, CONVERT_RNDSAT,
// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
// promotions and truncation for half-precision (16 bit) floating
// numbers. We need special nodes since FP16 is a storage-only type with
// special semantics of operations.
FP16_TO_FP32, FP32_TO_FP16,
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FLOG, FLOG2, FLOG10, FEXP, FEXP2, // FLOG, FLOG2, FLOG10, FEXP, FEXP2,
// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating // FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating

8
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@@ -4000,6 +4000,14 @@ SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
case Intrinsic::pow: case Intrinsic::pow:
visitPow(I); visitPow(I);
return 0; return 0;
case Intrinsic::convert_to_fp16:
setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
MVT::i16, getValue(I.getOperand(1))));
return 0;
case Intrinsic::convert_from_fp16:
setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
MVT::f32, getValue(I.getOperand(1))));
return 0;
case Intrinsic::pcmarker: { case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1)); SDValue Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));