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During two-address lowering, rescheduling an instruction does not untie
operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1248,7 +1248,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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// re-schedule this MI below it.
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if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
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++NumReSchedDowns;
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return true;
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return false;
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}
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if (TargetRegisterInfo::isVirtualRegister(regA))
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@ -1270,7 +1270,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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// re-schedule it before this MI if it's legal.
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if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
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++NumReSchedUps;
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return true;
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return false;
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}
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// If this is an instruction with a load folded into it, try unfolding
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24
test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
Normal file
24
test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
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@ -0,0 +1,24 @@
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; RUN: llc < %s
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; PR11861
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-gnueabi"
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define arm_aapcs_vfpcc void @foo() nounwind align 2 {
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br i1 undef, label %5, label %1
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; <label>:1 ; preds = %0
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%2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%3 = bitcast <2 x i64> %2 to <4 x float>
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store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
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store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
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store <4 x float> %3, <4 x float>* undef, align 16, !tbaa !0
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%4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
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store <4 x float> %4, <4 x float>* undef, align 16, !tbaa !0
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unreachable
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; <label>:5 ; preds = %0
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ret void
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}
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!0 = metadata !{metadata !"omnipotent char", metadata !1}
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!1 = metadata !{metadata !"Simple C/C++ TBAA", null}
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