6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-23 02:32:11 +00:00
Code Issues Projects Releases Wiki Activity

ARM fix encoding fixup resolution for ldrd and friends.

Browse Source 
The 8-bit payload is not contiguous in the opcode. Move the upper nibble
over 4 bits into the correct place.

rdar://11158641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-03-30 21:54:22 +00:00
parent c19f72bd83
commit bf3c322640
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -469,7 +469,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value = -Value; Value = -Value;
isAdd = false; isAdd = false;
} }
// The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
assert ((Value < 256) && "Out of range pc-relative fixup value!"); assert ((Value < 256) && "Out of range pc-relative fixup value!");
Value = (Value & 0xf) | ((Value & 0xf0) << 4);
return Value | (isAdd << 23); return Value | (isAdd << 23);
} }
case ARM::fixup_arm_pcrel_10: case ARM::fixup_arm_pcrel_10: