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add a small simplification that can be exposed after promotion/expansion

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22691 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-07 05:00:44 +00:00
parent ce869ee05b
commit bf3fa976ee
1 changed files with 7 additions and 2 deletions
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9
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -770,8 +770,6 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
// If we know the result of a setcc has the top bits zero, use this info.
switch (Op.getOpcode()) {
case ISD::UNDEF:
return true;
case ISD::Constant:
return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
@ -1044,6 +1042,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT());
if ((C2 & (~0ULL << ExtendBits)) == 0)
return getNode(ISD::AND, VT, N1.getOperand(0), N2);
} else if (N1.getOpcode() == ISD::OR) {
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
if ((ORI->getValue() & C2) == C2) {
// If the 'or' is setting all of the bits that we are masking for,
// we know the result of the AND will be the AND mask itself.
return N2;
}
}
break;
case ISD::OR: