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Treat external variables similarly to those with weak linkage: load indirect.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15047 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-20 20:43:05 +00:00
parent 1d3a8b0bd8
commit bf417a6d46
2 changed files with 8 additions and 8 deletions
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8
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -524,9 +524,8 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
// GV is located at PC + distance // GV is located at PC + distance
unsigned CurPC = makeAnotherReg(Type::IntTy); unsigned CurPC = makeAnotherReg(Type::IntTy);
unsigned TmpReg = makeAnotherReg(GV->getType()); unsigned TmpReg = makeAnotherReg(GV->getType());
unsigned Opcode = GV->hasWeakLinkage() ? unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()) ?
PPC32::LOADLoIndirect : PPC32::LOADLoIndirect : PPC32::LOADLoDirect;
PPC32::LOADLoDirect;
// Move PC to destination reg // Move PC to destination reg
BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC); BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
@ -2481,7 +2480,8 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
unsigned SrcReg2 = makeAnotherReg(Type::IntTy); unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1); BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1); BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2); BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg)
.addReg(SrcReg2);
break; break;
} }
case cFP32: case cFP32:

8
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

@ -524,9 +524,8 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
// GV is located at PC + distance // GV is located at PC + distance
unsigned CurPC = makeAnotherReg(Type::IntTy); unsigned CurPC = makeAnotherReg(Type::IntTy);
unsigned TmpReg = makeAnotherReg(GV->getType()); unsigned TmpReg = makeAnotherReg(GV->getType());
unsigned Opcode = GV->hasWeakLinkage() ? unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()) ?
PPC32::LOADLoIndirect : PPC32::LOADLoIndirect : PPC32::LOADLoDirect;
PPC32::LOADLoDirect;
// Move PC to destination reg // Move PC to destination reg
BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC); BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
@ -2481,7 +2480,8 @@ void ISel::emitCastOperation(MachineBasicBlock *MBB,
unsigned SrcReg2 = makeAnotherReg(Type::IntTy); unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1); BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1); BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2); BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg)
.addReg(SrcReg2);
break; break;
} }
case cFP32: case cFP32: