From bf63022492e54c8abe7c8d8c8448661342294f46 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 13 Mar 2014 23:12:04 +0000 Subject: [PATCH] Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineRegisterInfo.h | 128 ++++++++++++++++-- lib/CodeGen/LiveDebugVariables.cpp | 4 +- lib/CodeGen/LiveInterval.cpp | 4 +- lib/CodeGen/LiveRangeCalc.cpp | 8 +- lib/CodeGen/LiveRangeEdit.cpp | 4 +- lib/CodeGen/MachineCSE.cpp | 34 ++--- lib/CodeGen/MachineLICM.cpp | 10 +- lib/CodeGen/MachineRegisterInfo.cpp | 29 ++-- lib/CodeGen/MachineSink.cpp | 8 +- lib/CodeGen/MachineTraceMetrics.cpp | 2 +- lib/CodeGen/OptimizePHIs.cpp | 4 +- lib/CodeGen/PHIElimination.cpp | 5 +- lib/CodeGen/PHIEliminationUtils.cpp | 10 +- lib/CodeGen/PeepholeOptimizer.cpp | 14 +- lib/CodeGen/ProcessImplicitDefs.cpp | 2 +- lib/CodeGen/RegAllocFast.cpp | 4 +- lib/CodeGen/RegisterCoalescer.cpp | 8 +- lib/CodeGen/SelectionDAG/FastISel.cpp | 2 +- lib/CodeGen/Spiller.cpp | 9 +- lib/CodeGen/SplitKit.cpp | 6 +- lib/CodeGen/TailDuplication.cpp | 8 +- lib/CodeGen/TwoAddressInstructionPass.cpp | 12 +- lib/CodeGen/VirtRegMap.cpp | 6 +- lib/Target/ARM/A15SDOptimizer.cpp | 8 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 +- lib/Target/ARM/MLxExpansionPass.cpp | 4 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 10 +- lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 +- lib/Target/PowerPC/PPCInstrInfo.cpp | 17 +-- .../R600/R600OptimizeVectorRegisters.cpp | 17 +-- lib/Target/R600/SIFixSGPRCopies.cpp | 4 +- lib/Target/R600/SIInstrInfo.cpp | 2 +- lib/Target/X86/X86FrameLowering.cpp | 5 +- lib/Target/X86/X86ISelLowering.cpp | 4 +- lib/Target/X86/X86InstrInfo.cpp | 6 +- 35 files changed, 255 insertions(+), 150 deletions(-) diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index 7167595ec7d..dd9e2803bd2 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -203,10 +203,17 @@ public: template class defusechain_iterator; + template + class defusechain_instr_iterator; // Make it a friend so it can access getNextOperandForReg(). template friend class defusechain_iterator; + template + friend class defusechain_instr_iterator; + + /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified /// register. @@ -219,7 +226,7 @@ public: /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses /// of the specified register, stepping by MachineInstr. - typedef defusechain_iterator + typedef defusechain_instr_iterator reg_instr_iterator; reg_instr_iterator reg_instr_begin(unsigned RegNo) const { return reg_instr_iterator(getRegUseDefListHead(RegNo)); @@ -228,7 +235,7 @@ public: /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses /// of the specified register, stepping by bundle. - typedef defusechain_iterator + typedef defusechain_instr_iterator reg_bundle_iterator; reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const { return reg_bundle_iterator(getRegUseDefListHead(RegNo)); @@ -251,7 +258,7 @@ public: /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk /// all defs and uses of the specified register, stepping by MachineInstr, /// skipping those marked as Debug. - typedef defusechain_iterator + typedef defusechain_instr_iterator reg_instr_nodbg_iterator; reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const { return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); @@ -263,7 +270,7 @@ public: /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk /// all defs and uses of the specified register, stepping by bundle, /// skipping those marked as Debug. - typedef defusechain_iterator + typedef defusechain_instr_iterator reg_bundle_nodbg_iterator; reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const { return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); @@ -288,7 +295,7 @@ public: /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the /// specified register, stepping by MachineInst. - typedef defusechain_iterator + typedef defusechain_instr_iterator def_instr_iterator; def_instr_iterator def_instr_begin(unsigned RegNo) const { return def_instr_iterator(getRegUseDefListHead(RegNo)); @@ -297,7 +304,7 @@ public: /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the /// specified register, stepping by bundle. - typedef defusechain_iterator + typedef defusechain_instr_iterator def_bundle_iterator; def_bundle_iterator def_bundle_begin(unsigned RegNo) const { return def_bundle_iterator(getRegUseDefListHead(RegNo)); @@ -327,7 +334,7 @@ public: /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the /// specified register, stepping by MachineInstr. - typedef defusechain_iterator + typedef defusechain_instr_iterator use_instr_iterator; use_instr_iterator use_instr_begin(unsigned RegNo) const { return use_instr_iterator(getRegUseDefListHead(RegNo)); @@ -336,7 +343,7 @@ public: /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the /// specified register, stepping by bundle. - typedef defusechain_iterator + typedef defusechain_instr_iterator use_bundle_iterator; use_bundle_iterator use_bundle_begin(unsigned RegNo) const { return use_bundle_iterator(getRegUseDefListHead(RegNo)); @@ -368,7 +375,7 @@ public: /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk /// all uses of the specified register, stepping by MachineInstr, skipping /// those marked as Debug. - typedef defusechain_iterator + typedef defusechain_instr_iterator use_instr_nodbg_iterator; use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const { return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); @@ -380,7 +387,7 @@ public: /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk /// all uses of the specified register, stepping by bundle, skipping /// those marked as Debug. - typedef defusechain_iterator + typedef defusechain_instr_iterator use_bundle_nodbg_iterator; use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const { return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); @@ -743,11 +750,6 @@ public: defusechain_iterator tmp = *this; ++*this; return tmp; } - MachineOperand &getOperand() const { - assert(Op && "Cannot dereference end iterator!"); - return *Op; - } - /// getOperandNo - Return the operand # of this MachineOperand in its /// MachineInstr. unsigned getOperandNo() const { @@ -755,6 +757,102 @@ public: return Op - &Op->getParent()->getOperand(0); } + // Retrieve a reference to the current operand. + MachineOperand &operator*() const { + assert(Op && "Cannot dereference end iterator!"); + return *Op; + } + + MachineOperand *operator->() const { + assert(Op && "Cannot dereference end iterator!"); + return Op; + } + }; + + /// defusechain_iterator - This class provides iterator support for machine + /// operands in the function that use or define a specific register. If + /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it + /// returns defs. If neither are true then you are silly and it always + /// returns end(). If SkipDebug is true it skips uses marked Debug + /// when incrementing. + template + class defusechain_instr_iterator + : public std::iterator { + MachineOperand *Op; + explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { + // If the first node isn't one we're interested in, advance to one that + // we are interested in. + if (op) { + if ((!ReturnUses && op->isUse()) || + (!ReturnDefs && op->isDef()) || + (SkipDebug && op->isDebug())) + advance(); + } + } + friend class MachineRegisterInfo; + + void advance() { + assert(Op && "Cannot increment end iterator!"); + Op = getNextOperandForReg(Op); + + // All defs come before the uses, so stop def_iterator early. + if (!ReturnUses) { + if (Op) { + if (Op->isUse()) + Op = 0; + else + assert(!Op->isDebug() && "Can't have debug defs"); + } + } else { + // If this is an operand we don't care about, skip it. + while (Op && ((!ReturnDefs && Op->isDef()) || + (SkipDebug && Op->isDebug()))) + Op = getNextOperandForReg(Op); + } + } + public: + typedef std::iterator::reference reference; + typedef std::iterator::pointer pointer; + + defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){} + defusechain_instr_iterator() : Op(0) {} + + bool operator==(const defusechain_instr_iterator &x) const { + return Op == x.Op; + } + bool operator!=(const defusechain_instr_iterator &x) const { + return !operator==(x); + } + + /// atEnd - return true if this iterator is equal to reg_end() on the value. + bool atEnd() const { return Op == 0; } + + // Iterator traversal: forward iteration only + defusechain_instr_iterator &operator++() { // Preincrement + assert(Op && "Cannot increment end iterator!"); + if (ByOperand) + advance(); + else if (ByInstr) { + MachineInstr *P = Op->getParent(); + do { + advance(); + } while (Op && Op->getParent() == P); + } else if (ByBundle) { + MachineInstr *P = getBundleStart(Op->getParent()); + do { + advance(); + } while (Op && getBundleStart(Op->getParent()) == P); + } + + return *this; + } + defusechain_instr_iterator operator++(int) { // Postincrement + defusechain_instr_iterator tmp = *this; ++*this; return tmp; + } + // Retrieve a reference to the current operand. MachineInstr &operator*() const { assert(Op && "Cannot dereference end iterator!"); diff --git a/lib/CodeGen/LiveDebugVariables.cpp b/lib/CodeGen/LiveDebugVariables.cpp index fd7b309fb72..317f54461eb 100644 --- a/lib/CodeGen/LiveDebugVariables.cpp +++ b/lib/CodeGen/LiveDebugVariables.cpp @@ -571,10 +571,10 @@ UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo, for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(LI->reg), UE = MRI.use_nodbg_end(); UI != UE; ++UI) { + MachineInstr *MI = UI->getParent(); // Copies of the full value. - if (UI.getOperand().getSubReg() || !UI->isCopy()) + if (UI->getSubReg() || !MI->isCopy()) continue; - MachineInstr *MI = &*UI; unsigned DstReg = MI->getOperand(0).getReg(); // Don't follow copies to physregs. These are usually setting up call diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index 36b34520457..3a7ac11d42d 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -905,8 +905,8 @@ void ConnectedVNInfoEqClasses::Distribute(LiveInterval *LIV[], // Rewrite instructions. for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg), RE = MRI.reg_end(); RI != RE;) { - MachineOperand &MO = RI.getOperand(); - MachineInstr *MI = MO.getParent(); + MachineOperand &MO = *RI; + MachineInstr *MI = RI->getParent(); ++RI; // DBG_VALUE instructions don't have slot indexes, so get the index of the // instruction before them. diff --git a/lib/CodeGen/LiveRangeCalc.cpp b/lib/CodeGen/LiveRangeCalc.cpp index f81beadb595..4c7723c38f2 100644 --- a/lib/CodeGen/LiveRangeCalc.cpp +++ b/lib/CodeGen/LiveRangeCalc.cpp @@ -43,7 +43,7 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { // LR.createDeadDef() will deduplicate. for (MachineRegisterInfo::def_iterator I = MRI->def_begin(Reg), E = MRI->def_end(); I != E; ++I) { - const MachineInstr *MI = &*I; + const MachineInstr *MI = I->getParent(); // Find the corresponding slot index. SlotIndex Idx; if (MI->isPHI()) @@ -52,7 +52,7 @@ void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) { else // Instructions are either normal 'r', or early clobber 'e'. Idx = Indexes->getInstructionIndex(MI) - .getRegSlot(I.getOperand().isEarlyClobber()); + .getRegSlot(I->isEarlyClobber()); // Create the def in LR. This may find an existing def. LR.createDeadDef(Idx, *Alloc); @@ -66,7 +66,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { // Visit all operands that read Reg. This may include partial defs. for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg), E = MRI->reg_nodbg_end(); I != E; ++I) { - MachineOperand &MO = I.getOperand(); + MachineOperand &MO = *I; // Clear all kill flags. They will be reinserted after register allocation // by LiveIntervalAnalysis::addKillFlags(). if (MO.isUse()) @@ -75,7 +75,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg) { continue; // MI is reading Reg. We may have visited MI before if it happens to be // reading Reg multiple times. That is OK, extend() is idempotent. - const MachineInstr *MI = &*I; + const MachineInstr *MI = I->getParent(); // Find the SlotIndex being read. SlotIndex Idx; diff --git a/lib/CodeGen/LiveRangeEdit.cpp b/lib/CodeGen/LiveRangeEdit.cpp index cb70c43bf55..c7372592854 100644 --- a/lib/CodeGen/LiveRangeEdit.cpp +++ b/lib/CodeGen/LiveRangeEdit.cpp @@ -169,8 +169,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, // Check that there is a single def and a single use. for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg), E = MRI.reg_nodbg_end(); I != E; ++I) { - MachineOperand &MO = I.getOperand(); - MachineInstr *MI = MO.getParent(); + MachineOperand &MO = *I; + MachineInstr *MI = I->getParent(); if (MO.isDef()) { if (DefMI && DefMI != MI) return false; diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index b5c39958240..76ab7dcb6a3 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -364,15 +364,15 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, TargetRegisterInfo::isVirtualRegister(Reg)) { MayIncreasePressure = false; SmallPtrSet CSUses; - for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg), - E = MRI->use_nodbg_end(); I != E; ++I) { - MachineInstr *Use = &*I; - CSUses.insert(Use); + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end(); + I != E; ++I) { + CSUses.insert(&*I); } - for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), - E = MRI->use_nodbg_end(); I != E; ++I) { - MachineInstr *Use = &*I; - if (!CSUses.count(Use)) { + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); + I != E; ++I) { + if (!CSUses.count(&*I)) { MayIncreasePressure = true; break; } @@ -403,11 +403,11 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, } if (!HasVRegUse) { bool HasNonCopyUse = false; - for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), - E = MRI->use_nodbg_end(); I != E; ++I) { - MachineInstr *Use = &*I; + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); + I != E; ++I) { // Ignore copies. - if (!Use->isCopyLike()) { + if (!I->isCopyLike()) { HasNonCopyUse = true; break; } @@ -420,11 +420,11 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg, // it unless the defined value is already used in the BB of the new use. bool HasPHI = false; SmallPtrSet CSBBs; - for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg), - E = MRI->use_nodbg_end(); I != E; ++I) { - MachineInstr *Use = &*I; - HasPHI |= Use->isPHI(); - CSBBs.insert(Use->getParent()); + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(CSReg), E = MRI->use_instr_nodbg_end(); + I != E; ++I) { + HasPHI |= I->isPHI(); + CSBBs.insert(I->getParent()); } if (!HasPHI) diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 75271d1e946..9fcf11396fa 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -978,8 +978,9 @@ bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const { unsigned Reg = MO->getReg(); if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), - UE = MRI->use_end(); UI != UE; ++UI) { + for (MachineRegisterInfo::use_instr_iterator + UI = MRI->use_instr_begin(Reg), UE = MRI->use_instr_end(); + UI != UE; ++UI) { MachineInstr *UseMI = &*UI; // A PHI may cause a copy to be inserted. if (UseMI->isPHI()) { @@ -1011,8 +1012,9 @@ bool MachineLICM::HasHighOperandLatency(MachineInstr &MI, if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg)) return false; - for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), - E = MRI->use_nodbg_end(); I != E; ++I) { + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); + I != E; ++I) { MachineInstr *UseMI = &*I; if (UseMI->isCopyLike()) continue; diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index 3dabcbed7fc..094cf84dd3a 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -80,8 +80,9 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; ++I) { // Apply the effect of the given operand to NewRC. - NewRC = I->getRegClassConstraintEffect(I.getOperandNo(), NewRC, TII, - getTargetRegisterInfo()); + MachineInstr *MI = I->getParent(); + NewRC = MI->getRegClassConstraintEffect(I.getOperandNo(), NewRC, TII, + getTargetRegisterInfo()); if (!NewRC || NewRC == OldRC) return false; } @@ -126,7 +127,7 @@ void MachineRegisterInfo::verifyUseList(unsigned Reg) const { #ifndef NDEBUG bool Valid = true; for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { - MachineOperand *MO = &I.getOperand(); + MachineOperand *MO = &*I; MachineInstr *MI = MO->getParent(); if (!MI) { errs() << PrintReg(Reg, getTargetRegisterInfo()) @@ -287,7 +288,7 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { // TODO: This could be more efficient by bulk changing the operands. for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { - MachineOperand &O = I.getOperand(); + MachineOperand &O = *I; ++I; O.setReg(ToReg); } @@ -299,8 +300,8 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { /// form, so there should only be one definition. MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { // Since we are in SSA form, we can use the first definition. - def_iterator I = def_begin(Reg); - assert((I.atEnd() || std::next(I) == def_end()) && + def_instr_iterator I = def_instr_begin(Reg); + assert((I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition"); return !I.atEnd() ? &*I : 0; } @@ -310,8 +311,8 @@ MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { /// multiple definitions or no definition, return null. MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { if (def_empty(Reg)) return 0; - def_iterator I = def_begin(Reg); - if (std::next(I) != def_end()) + def_instr_iterator I = def_instr_begin(Reg); + if (std::next(I) != def_instr_end()) return 0; return &*I; } @@ -329,7 +330,7 @@ bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { /// preserve conservative kill flag information. void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) - UI.getOperand().setIsKill(false); + UI->setIsKill(false); } bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { @@ -392,7 +393,7 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, #ifndef NDEBUG void MachineRegisterInfo::dumpUses(unsigned Reg) const { for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) - I.getOperand().getParent()->dump(); + I->getParent()->dump(); } #endif @@ -420,11 +421,11 @@ bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, /// deleted during LiveDebugVariables analysis. void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) - MachineRegisterInfo::use_iterator nextI; - for (use_iterator I = use_begin(Reg), E = use_end(); I != E; I = nextI) { + MachineRegisterInfo::use_instr_iterator nextI; + for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); + I != E; I = nextI) { nextI = std::next(I); // I is invalidated by the setReg - MachineOperand& Use = I.getOperand(); - MachineInstr *UseMI = Use.getParent(); + MachineInstr *UseMI = &*I; if (UseMI->isDebugValue()) UseMI->getOperand(0).setReg(0U); } diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 0a74f11b561..4523753eba5 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -174,7 +174,7 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); I != E; ++I) { - MachineInstr *UseInst = &*I; + MachineInstr *UseInst = I->getParent(); MachineBasicBlock *UseBlock = UseInst->getParent(); if (!(UseBlock == MBB && UseInst->isPHI() && UseInst->getOperand(I.getOperandNo()+1).getMBB() == DefMBB)) { @@ -189,7 +189,7 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); I != E; ++I) { // Determine the block of the use. - MachineInstr *UseInst = &*I; + MachineInstr *UseInst = I->getParent(); MachineBasicBlock *UseBlock = UseInst->getParent(); if (UseInst->isPHI()) { // PHI nodes use the operand in the predecessor block, not the block with @@ -450,8 +450,8 @@ bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI, // Check if only use in post dominated block is PHI instruction. bool NonPHIUse = false; - for (MachineRegisterInfo::use_nodbg_iterator - I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); + for (MachineRegisterInfo::use_instr_nodbg_iterator + I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); I != E; ++I) { MachineInstr *UseInst = &*I; MachineBasicBlock *UseBlock = UseInst->getParent(); diff --git a/lib/CodeGen/MachineTraceMetrics.cpp b/lib/CodeGen/MachineTraceMetrics.cpp index b10e778cc8e..d07178e71f0 100644 --- a/lib/CodeGen/MachineTraceMetrics.cpp +++ b/lib/CodeGen/MachineTraceMetrics.cpp @@ -627,7 +627,7 @@ struct DataDep { assert(TargetRegisterInfo::isVirtualRegister(VirtReg)); MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); assert(!DefI.atEnd() && "Register has no defs"); - DefMI = &*DefI; + DefMI = DefI->getParent(); DefOp = DefI.getOperandNo(); assert((++DefI).atEnd() && "Register has multiple defs"); } diff --git a/lib/CodeGen/OptimizePHIs.cpp b/lib/CodeGen/OptimizePHIs.cpp index 748a59c3c96..50968efc9d5 100644 --- a/lib/CodeGen/OptimizePHIs.cpp +++ b/lib/CodeGen/OptimizePHIs.cpp @@ -139,8 +139,8 @@ bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) { if (PHIsInCycle.size() == 16) return false; - for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg), - E = MRI->use_end(); I != E; ++I) { + for (MachineRegisterInfo::use_instr_iterator I = MRI->use_instr_begin(DstReg), + E = MRI->use_instr_end(); I != E; ++I) { MachineInstr *UseMI = &*I; if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle)) return false; diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index e62625d1c92..cff80317d13 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -198,8 +198,9 @@ bool PHIElimination::EliminatePHINodes(MachineFunction &MF, /// This includes registers with no defs. static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI) { - for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg), - DE = MRI->def_end(); DI != DE; ++DI) + for (MachineRegisterInfo::def_instr_iterator + DI = MRI->def_instr_begin(VirtReg), DE = MRI->def_instr_end(); + DI != DE; ++DI) if (!DI->isImplicitDef()) return false; return true; diff --git a/lib/CodeGen/PHIEliminationUtils.cpp b/lib/CodeGen/PHIEliminationUtils.cpp index e1b56e962fa..14cb94b05ba 100644 --- a/lib/CodeGen/PHIEliminationUtils.cpp +++ b/lib/CodeGen/PHIEliminationUtils.cpp @@ -34,11 +34,11 @@ llvm::findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, // Discover any defs/uses in this basic block. SmallPtrSet DefUsesInMBB; MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); - for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), - RE = MRI.reg_end(); RI != RE; ++RI) { - MachineInstr* DefUseMI = &*RI; - if (DefUseMI->getParent() == MBB) - DefUsesInMBB.insert(DefUseMI); + for (MachineRegisterInfo::reg_instr_iterator + RI = MRI.reg_instr_begin(SrcReg), RE = MRI.reg_instr_end(); + RI != RE; ++RI) { + if (RI->getParent() == MBB) + DefUsesInMBB.insert(&*RI); } MachineBasicBlock::iterator InsertPoint; diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index 8bf2270755e..eac72599a2a 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -187,8 +187,8 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, // The source has other uses. See if we can replace the other uses with use of // the result of the extension. SmallPtrSet ReachedBBs; - for (MachineRegisterInfo::use_nodbg_iterator - UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); + for (MachineRegisterInfo::use_instr_nodbg_iterator + UI = MRI->use_instr_nodbg_begin(DstReg), UE = MRI->use_instr_nodbg_end(); UI != UE; ++UI) ReachedBBs.insert(UI->getParent()); @@ -202,8 +202,8 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineOperand &UseMO = UI.getOperand(); - MachineInstr *UseMI = &*UI; + MachineOperand &UseMO = *UI; + MachineInstr *UseMI = UseMO.getParent(); if (UseMI == MI) continue; @@ -270,9 +270,9 @@ optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, // Look for PHI uses of the extended result, we don't want to extend the // liveness of a PHI input. It breaks all kinds of assumptions down // stream. A PHI use is expected to be the kill of its source values. - for (MachineRegisterInfo::use_nodbg_iterator - UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); - UI != UE; ++UI) + for (MachineRegisterInfo::use_instr_nodbg_iterator + UI = MRI->use_instr_nodbg_begin(DstReg), + UE = MRI->use_instr_nodbg_end(); UI != UE; ++UI) if (UI->isPHI()) PHIBBs.insert(UI->getParent()); diff --git a/lib/CodeGen/ProcessImplicitDefs.cpp b/lib/CodeGen/ProcessImplicitDefs.cpp index a0d3416febf..84503b5aab8 100644 --- a/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/lib/CodeGen/ProcessImplicitDefs.cpp @@ -83,7 +83,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineOperand &MO = UI.getOperand(); + MachineOperand &MO = *UI; MO.setIsUndef(); MachineInstr *UserMI = MO.getParent(); if (!canTurnIntoImplicitDef(UserMI)) diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 08b8dd037af..8dc44f546aa 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -224,7 +224,7 @@ bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { // Check that the use/def chain has exactly one operand - MO. MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg()); - if (&I.getOperand() != &MO) + if (&*I != &MO) return false; return ++I == MRI->reg_nodbg_end(); } @@ -590,7 +590,7 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, // If there is no hint, peek at the only use of this register. if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) && MRI->hasOneNonDBGUse(VirtReg)) { - const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg); + const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg); // It's a copy, use the destination register as a hint. if (UseMI.isCopyLike()) Hint = UseMI.getOperand(0).getReg(); diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 13ea1a58e04..727f50ff5a3 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -624,7 +624,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(IntA.reg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineInstr *UseMI = &*UI; + MachineInstr *UseMI = UI->getParent(); SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); if (US == IntA.end() || US->valno != AValNo) @@ -668,8 +668,8 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, // Update uses of IntA of the specific Val# with IntB. for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg), UE = MRI->use_end(); UI != UE;) { - MachineOperand &UseMO = UI.getOperand(); - MachineInstr *UseMI = &*UI; + MachineOperand &UseMO = *UI; + MachineInstr *UseMI = UseMO.getParent(); ++UI; if (UseMI->isDebugValue()) { // FIXME These don't have an instruction index. Not clear we have enough @@ -914,7 +914,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI, for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end(); I != E; ++I) { - MachineOperand &MO = I.getOperand(); + MachineOperand &MO = *I; if (MO.isDef() || MO.isUndef()) continue; MachineInstr *MI = MO.getParent(); diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index 6ae431b8aa2..baba51eaf28 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1559,7 +1559,7 @@ bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) { return false; MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg); - MachineInstr *User = &*RI; + MachineInstr *User = RI->getParent(); // Set the insertion point properly. Folding the load can cause generation of // other random instructions (like sign extends) for addressing modes; make diff --git a/lib/CodeGen/Spiller.cpp b/lib/CodeGen/Spiller.cpp index c5923f932c3..094641ce93f 100644 --- a/lib/CodeGen/Spiller.cpp +++ b/lib/CodeGen/Spiller.cpp @@ -89,8 +89,9 @@ protected: unsigned ss = vrm->assignVirt2StackSlot(li->reg); // Iterate over reg uses/defs. - for (MachineRegisterInfo::reg_iterator - regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) { + for (MachineRegisterInfo::reg_instr_iterator + regItr = mri->reg_instr_begin(li->reg); + regItr != mri->reg_instr_end();) { // Grab the use/def instr. MachineInstr *mi = &*regItr; @@ -98,9 +99,7 @@ protected: DEBUG(dbgs() << " Processing " << *mi); // Step regItr to the next use/def instr. - do { - ++regItr; - } while (regItr != mri->reg_end() && (&*regItr == mi)); + ++regItr; // Collect uses & defs for this instr. SmallVector indices; diff --git a/lib/CodeGen/SplitKit.cpp b/lib/CodeGen/SplitKit.cpp index 69f27ccb82f..1e0f1e14d4a 100644 --- a/lib/CodeGen/SplitKit.cpp +++ b/lib/CodeGen/SplitKit.cpp @@ -134,8 +134,8 @@ void SplitAnalysis::analyzeUses() { for (MachineRegisterInfo::use_nodbg_iterator I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E; ++I) - if (!I.getOperand().isUndef()) - UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot()); + if (!I->isUndef()) + UseSlots.push_back(LIS.getInstructionIndex(I->getParent()).getRegSlot()); array_pod_sort(UseSlots.begin(), UseSlots.end()); @@ -972,7 +972,7 @@ void SplitEditor::extendPHIKillRanges() { void SplitEditor::rewriteAssigned(bool ExtendRanges) { for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()), RE = MRI.reg_end(); RI != RE;) { - MachineOperand &MO = RI.getOperand(); + MachineOperand &MO = *RI; MachineInstr *MI = MO.getParent(); ++RI; // LiveDebugVariables should have handled all DBG_VALUE instructions. diff --git a/lib/CodeGen/TailDuplication.cpp b/lib/CodeGen/TailDuplication.cpp index 2fd589008d0..df28c3938ad 100644 --- a/lib/CodeGen/TailDuplication.cpp +++ b/lib/CodeGen/TailDuplication.cpp @@ -262,8 +262,8 @@ TailDuplicatePass::TailDuplicateAndUpdate(MachineBasicBlock *MBB, // Rewrite uses that are outside of the original def's block. MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg); while (UI != MRI->use_end()) { - MachineOperand &UseMO = UI.getOperand(); - MachineInstr *UseMI = &*UI; + MachineOperand &UseMO = *UI; + MachineInstr *UseMI = UseMO.getParent(); ++UI; if (UseMI->isDebugValue()) { // SSAUpdate can replace the use with an undef. That creates @@ -338,8 +338,8 @@ bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) { static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI) { - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), - UE = MRI->use_end(); UI != UE; ++UI) { + for (MachineRegisterInfo::use_instr_iterator UI = MRI->use_instr_begin(Reg), + UE = MRI->use_instr_end(); UI != UE; ++UI) { MachineInstr *UseMI = &*UI; if (UseMI->isDebugValue()) continue; diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 9baf1ff0582..4fbf068b671 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -229,7 +229,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SavedReg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { - MachineOperand &UseMO = UI.getOperand(); + MachineOperand &UseMO = *UI; if (!UseMO.isKill()) continue; KillMI = UseMO.getParent(); @@ -317,7 +317,7 @@ bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned LastUse = Dist; for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), E = MRI->reg_end(); I != E; ++I) { - MachineOperand &MO = I.getOperand(); + MachineOperand &MO = *I; MachineInstr *MI = MO.getParent(); if (MI->getParent() != MBB || MI->isDebugValue()) continue; @@ -419,7 +419,7 @@ static bool isKilled(MachineInstr &MI, unsigned Reg, // go with what the kill flag says. if (std::next(Begin) != MRI->def_end()) return true; - DefMI = &*Begin; + DefMI = Begin->getParent(); bool IsSrcPhys, IsDstPhys; unsigned SrcReg, DstReg; // If the def is something other than a copy, then it isn't going to @@ -457,7 +457,7 @@ MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, if (!MRI->hasOneNonDBGUse(Reg)) // None or more than one use. return 0; - MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); + MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg); if (UseMI.getParent() != MBB) return 0; unsigned SrcReg; @@ -914,8 +914,8 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, /// instruction too close to the defs of its register dependencies. bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) { - for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg), - DE = MRI->def_end(); DI != DE; ++DI) { + for (MachineRegisterInfo::def_instr_iterator DI = MRI->def_instr_begin(Reg), + DE = MRI->def_instr_end(); DI != DE; ++DI) { MachineInstr *DefMI = &*DI; if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) continue; diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index f87c8b06d15..54bc6f8eb08 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -418,9 +418,9 @@ void VirtRegRewriter::rewrite() { // Check if this register has a use that will impact the rest of the // code. Uses in debug and noreturn instructions do not impact the // generated code. - for (MachineRegisterInfo::reg_nodbg_iterator It = - MRI->reg_nodbg_begin(Reg), - EndIt = MRI->reg_nodbg_end(); It != EndIt; ++It) { + for (MachineRegisterInfo::reg_instr_nodbg_iterator It = + MRI->reg_instr_nodbg_begin(Reg), + EndIt = MRI->reg_instr_nodbg_end(); It != EndIt; ++It) { if (!NoReturnInsts.count(&(*It))) { MRI->setPhysRegUsed(Reg); break; diff --git a/lib/Target/ARM/A15SDOptimizer.cpp b/lib/Target/ARM/A15SDOptimizer.cpp index 3fa204fb251..8edf00a70a6 100644 --- a/lib/Target/ARM/A15SDOptimizer.cpp +++ b/lib/Target/ARM/A15SDOptimizer.cpp @@ -225,9 +225,9 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { IsDead = false; break; } - for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg), - EE = MRI->use_end(); - II != EE; ++II) { + for (MachineRegisterInfo::use_instr_iterator + II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end(); + II != EE; ++II) { // We don't care about self references. if (&*II == Def) continue; @@ -646,7 +646,7 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) { unsigned DPRDefReg = MI->getOperand(0).getReg(); for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg), E = MRI->use_end(); I != E; ++I) - Uses.push_back(&I.getOperand()); + Uses.push_back(&*I); // We can optimize this. unsigned NewReg = optimizeSDPattern(MI); diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 14cc1fdba10..21b8e6b8705 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2245,8 +2245,9 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, if (CmpMask != ~0) { if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) { MI = 0; - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg), - UE = MRI->use_end(); UI != UE; ++UI) { + for (MachineRegisterInfo::use_instr_iterator + UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end(); + UI != UE; ++UI) { if (UI->getParent() != CmpInstr->getParent()) continue; MachineInstr *PotentialAND = &*UI; if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) || diff --git a/lib/Target/ARM/MLxExpansionPass.cpp b/lib/Target/ARM/MLxExpansionPass.cpp index fdb574aae8e..80af8591ea9 100644 --- a/lib/Target/ARM/MLxExpansionPass.cpp +++ b/lib/Target/ARM/MLxExpansionPass.cpp @@ -120,7 +120,7 @@ unsigned MLxExpansion::getDefReg(MachineInstr *MI) const { return Reg; MachineBasicBlock *MBB = MI->getParent(); - MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg); + MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg); if (UseMI->getParent() != MBB) return Reg; @@ -129,7 +129,7 @@ unsigned MLxExpansion::getDefReg(MachineInstr *MI) const { if (TargetRegisterInfo::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) return Reg; - UseMI = &*MRI->use_nodbg_begin(Reg); + UseMI = &*MRI->use_instr_nodbg_begin(Reg); if (UseMI->getParent() != MBB) return Reg; } diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index c94be7ec573..936fb11a38a 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -907,10 +907,10 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI, // this instruction is dead: both it (and the phi node) can be removed. use_nodbg_iterator I = MRI->use_nodbg_begin(Reg); use_nodbg_iterator End = MRI->use_nodbg_end(); - if (std::next(I) != End || !I.getOperand().getParent()->isPHI()) + if (std::next(I) != End || !I->getParent()->isPHI()) return false; - MachineInstr *OnePhi = I.getOperand().getParent(); + MachineInstr *OnePhi = I->getParent(); for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) { const MachineOperand &OPO = OnePhi->getOperand(j); if (!OPO.isReg() || !OPO.isDef()) @@ -921,7 +921,7 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI, for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J != End; J = nextJ) { nextJ = std::next(J); - MachineOperand &Use = J.getOperand(); + MachineOperand &Use = *J; MachineInstr *UseMI = Use.getParent(); // If the phi node has a user that is not MI, bail... @@ -955,8 +955,8 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) { for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) { nextI = std::next(I); // I is invalidated by the setReg - MachineOperand &Use = I.getOperand(); - MachineInstr *UseMI = Use.getParent(); + MachineOperand &Use = *I; + MachineInstr *UseMI = I->getParent(); if (UseMI == MI) continue; if (Use.isDebug()) diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 61dc454a0e0..ac550d13e79 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -104,7 +104,7 @@ bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, // Replace uses with ZeroReg. for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), E = MRI->use_end(); U != E;) { - MachineOperand &MO = U.getOperand(); + MachineOperand &MO = *U; unsigned OpNo = U.getOperandNo(); MachineInstr *MI = MO.getParent(); ++U; diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 408dd06b220..72c7118fcf8 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1323,8 +1323,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, if (equalityOnly) { // We need to check the uses of the condition register in order to reject // non-equality comparisons. - for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg), - IE = MRI->use_end(); I != IE; ++I) { + for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg), + IE = MRI->use_instr_end(); I != IE; ++I) { MachineInstr *UseMI = &*I; if (UseMI->getOpcode() == PPC::BCC) { unsigned Pred = UseMI->getOperand(0).getImm(); @@ -1346,8 +1346,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end(); I != EL; ++I) { bool FoundUse = false; - for (MachineRegisterInfo::use_iterator J = MRI->use_begin(CRReg), - JE = MRI->use_end(); J != JE; ++J) + for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg), + JE = MRI->use_instr_end(); J != JE; ++J) if (&*J == &*I) { FoundUse = true; break; @@ -1456,15 +1456,16 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, } if (ShouldSwap) - for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg), - IE = MRI->use_end(); I != IE; ++I) { + for (MachineRegisterInfo::use_instr_iterator + I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end(); + I != IE; ++I) { MachineInstr *UseMI = &*I; if (UseMI->getOpcode() == PPC::BCC) { PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); assert((!equalityOnly || Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) && "Invalid predicate for equality-only optimization"); - PredsToUpdate.push_back(std::make_pair(&((*I).getOperand(0)), + PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), PPC::getSwappedPredicate(Pred))); } else if (UseMI->getOpcode() == PPC::ISEL || UseMI->getOpcode() == PPC::ISEL8) { @@ -1477,7 +1478,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, else if (NewSubReg == PPC::sub_gt) NewSubReg = PPC::sub_lt; - SubRegsToUpdate.push_back(std::make_pair(&((*I).getOperand(3)), + SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)), NewSubReg)); } else // We need to abort on a user we don't understand. return false; diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp index 49a90658a77..767e5e37a42 100644 --- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp +++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp @@ -46,8 +46,8 @@ namespace { static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { - for (MachineRegisterInfo::def_iterator It = MRI.def_begin(Reg), - E = MRI.def_end(); It != E; ++It) { + for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), + E = MRI.def_instr_end(); It != E; ++It) { return (*It).isImplicitDef(); } if (MRI.isReserved(Reg)) { @@ -213,8 +213,8 @@ MachineInstr *R600VectorRegMerger::RebuildVector( DEBUG(dbgs() << " ->"; Pos->dump();); DEBUG(dbgs() << " Updating Swizzle:\n"); - for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), - E = MRI->use_end(); It != E; ++It) { + for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), + E = MRI->use_instr_end(); It != E; ++It) { DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->"); SwizzleInput(*It, RemapChan); DEBUG((*It).dump()); @@ -261,8 +261,8 @@ void R600VectorRegMerger::SwizzleInput(MachineInstr &MI, } bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { - for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), - E = MRI->use_end(); It != E; ++It) { + for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), + E = MRI->use_instr_end(); It != E; ++It) { if (!canSwizzle(*It)) return false; } @@ -328,8 +328,9 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) { if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { unsigned Reg = MI->getOperand(1).getReg(); - for (MachineRegisterInfo::def_iterator It = MRI->def_begin(Reg), - E = MRI->def_end(); It != E; ++It) { + for (MachineRegisterInfo::def_instr_iterator + It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); + It != E; ++It) { RemoveMI(&(*It)); } } diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp index f0065ea13c5..402f1f4d651 100644 --- a/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/lib/Target/R600/SIFixSGPRCopies.cpp @@ -141,8 +141,8 @@ const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses( const TargetRegisterClass *RC = MRI.getRegClass(Reg); RC = TRI->getSubRegClass(RC, SubReg); - for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), - E = MRI.use_end(); I != E; ++I) { + for (MachineRegisterInfo::use_instr_iterator + I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) { switch (I->getOpcode()) { case AMDGPU::COPY: RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 89054182d45..676e0388b0f 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -691,7 +691,7 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg), E = MRI.use_end(); I != E; ++I) { - MachineInstr &UseMI = *I; + MachineInstr &UseMI = *I->getParent(); if (!canReadVGPR(UseMI, I.getOperandNo())) { Worklist.push_back(&UseMI); } diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 0bdabb2fddd..5054d293cf0 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -379,8 +379,9 @@ void X86FrameLowering::emitCalleeSavedFrameMoves( static bool usesTheStack(const MachineFunction &MF) { const MachineRegisterInfo &MRI = MF.getRegInfo(); - for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS), - re = MRI.reg_end(); ri != re; ++ri) + for (MachineRegisterInfo::reg_instr_iterator + ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end(); + ri != re; ++ri) if (ri->isCopy()) return true; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e22a6a5c324..f227be19471 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -16131,7 +16131,7 @@ X86TargetLowering::emitFMA3Instr(MachineInstr *MI, // Check whether the addend is defined by a PHI: assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?"); - MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg()); + MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg()); if (!AddendDef.isPHI()) return MBB; @@ -16150,7 +16150,7 @@ X86TargetLowering::emitFMA3Instr(MachineInstr *MI, for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) { assert(AddendDef.getOperand(i).isReg()); MachineOperand PHISrcOp = AddendDef.getOperand(i); - MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg()); + MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg()); if (&PHISrcInst == MI) { // Found a matching instruction. unsigned NewFMAOpc = 0; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 20b95e7d19c..8eb4a17269b 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1619,9 +1619,9 @@ static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) return false; bool isPICBase = false; - for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), - E = MRI.def_end(); I != E; ++I) { - MachineInstr *DefMI = I.getOperand().getParent(); + for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), + E = MRI.def_instr_end(); I != E; ++I) { + MachineInstr *DefMI = &*I; if (DefMI->getOpcode() != X86::MOVPC32r) return false; assert(!isPICBase && "More than one PIC base?");