6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-27 13:30:05 +00:00
Code Issues Projects Releases Wiki Activity

This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2013-09-06 12:41:17 +00:00
parent a5eeb9da05
commit bf7f7b5e0e
7 changed files with 83 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -123,3 +123,18 @@ class LWL_FM_MM<bits<4> funct> {
let Inst{15-12} = funct;
let Inst{11-0} = addr{11-0};
}
class CMov_F_I_FM_MM<bits<7> func> : MMArch {
bits<5> rd;
bits<5> rs;
bits<3> fcc;
bits<32> Inst;
let Inst{31-26} = 0x15;
let Inst{25-21} = rd;
let Inst{20-16} = rs;
let Inst{15-13} = fcc;
let Inst{12-6} = func;
let Inst{5-0} = 0x3b;
}

10
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -109,4 +109,14 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>;
/// Move Conditional
def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
NoItinerary>, ADD_FM_MM<0, 0x58>;
def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
NoItinerary>, ADD_FM_MM<0, 0x18>;
def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIAlu>,
CMov_F_I_FM_MM<0x25>;
def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
CMov_F_I_FM_MM<0x5>;
}

14
lib/Target/Mips/MipsCondMov.td
View File

@ -19,7 +19,7 @@
class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
InstrItinClass Itin> :
InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
!strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
!strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
let Constraints = "$F = $rd";
}
@ -37,7 +37,7 @@ class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $fcc"),
[(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
Itin, FrmFR> {
Itin, FrmFR, opstr> {
let Constraints = "$F = $rd";
}
@ -103,7 +103,7 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
}
// Instantiation of instructions.
def MOVZ_I_I : CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>,
ADD_FM<0, 0xa>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
@ -115,8 +115,8 @@ let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
NoItinerary>, ADD_FM<0, 0xa>;
}
def MOVN_I_I : CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
NoItinerary>, ADD_FM<0, 0xb>;
def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
NoItinerary>, ADD_FM<0, 0xb>;
let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd,
@ -161,14 +161,14 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
}
}
def MOVT_I : CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>;
let isCodeGenOnly = 1 in
def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, IIArith, MipsCMovFP_T>,
CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>;
def MOVF_I : CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>,
def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>,
CMov_F_I_FM<0>;
let isCodeGenOnly = 1 in

2
lib/Target/Mips/MipsInstrFormats.td
View File

@ -730,7 +730,7 @@ class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
let Inst{5-0} = funct;
}
class CMov_F_I_FM<bit tf> {
class CMov_F_I_FM<bit tf> : StdArch {
bits<5> rd;
bits<5> rs;
bits<3> fcc;

12
test/MC/Disassembler/Mips/micromips.txt
View File

@ -147,3 +147,15 @@
# CHECK: swr $4, 16($5)
0x60 0x85 0x90 0x10
# CHECK: movz $9, $6, $7
0x00 0xe6 0x48 0x58
# CHECK: movn $9, $6, $7
0x00 0xe6 0x48 0x18
# CHECK: movt $9, $6, $fcc0
0x55 0x26 0x09 0x7b
# CHECK: movf $9, $6, $fcc0
0x55 0x26 0x01 0x7b

12
test/MC/Disassembler/Mips/micromips_le.txt
View File

@ -147,3 +147,15 @@
# CHECK: swr $4, 16($5)
0x85 0x60 0x10 0x90
# CHECK: movz $9, $6, $7
0xe6 0x00 0x58 0x48
# CHECK: movn $9, $6, $7
0xe6 0x00 0x18 0x48
# CHECK: movt $9, $6, $fcc0
0x26 0x55 0x7b 0x09
# CHECK: movf $9, $6, $fcc0
0x26 0x55 0x7b 0x01

26
test/MC/Mips/micromips-movcond-instructions.s Normal file
View File

@ -0,0 +1,26 @@
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
# RUN: | FileCheck -check-prefix=CHECK-EL %s
# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
# RUN: | FileCheck -check-prefix=CHECK-EB %s
# Check that the assembler can handle the documented syntax
# for move conditional instructions.
#------------------------------------------------------------------------------
# Move Conditional
#------------------------------------------------------------------------------
# Little endian
#------------------------------------------------------------------------------
# CHECK-EL: movz $9, $6, $7 # encoding: [0xe6,0x00,0x58,0x48]
# CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
# CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
# CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
# CHECK-EB: movz $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x58]
# CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
# CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
# CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
movz $9, $6, $7
movn $9, $6, $7
movt $9, $6, $fcc0
movf $9, $6, $fcc0