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Add a utility routine to check for unpredicated terminator instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-06-08 21:59:56 +00:00
parent 61718a6285
commit bfd2ec4a8e
6 changed files with 24 additions and 13 deletions
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8
include/llvm/Target/TargetInstrInfo.h
View File

@ -399,19 +399,23 @@ public:
abort(); abort();
} }
/// isPredicable - Returns true if the instruction is already predicated. /// isPredicated - Returns true if the instruction is already predicated.
/// ///
virtual bool isPredicated(const MachineInstr *MI) const { virtual bool isPredicated(const MachineInstr *MI) const {
return false; return false;
} }
/// isUnpredicatedTerminator - Returns true if the instruction is a
/// terminator instruction that has not been predicated.
bool isUnpredicatedTerminator(const MachineInstr *MI) const;
/// PredicateInstruction - Convert the instruction into a predicated /// PredicateInstruction - Convert the instruction into a predicated
/// instruction. It returns true if the operation was successful. /// instruction. It returns true if the operation was successful.
virtual virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const; const std::vector<MachineOperand> &Pred) const;
/// SubsumesPredicate - Returns true if the first specified predicated /// SubsumesPredicate - Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT. /// subsumes the second, e.g. GE subsumes GT.
virtual virtual
bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,

6
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -304,7 +304,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
std::vector<MachineOperand> &Cond) const { std::vector<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
return false; return false;
// Get the last instruction in the block. // Get the last instruction in the block.
@ -313,7 +313,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there is only one terminator instruction, process it. // If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode(); unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || if (I == MBB.begin() ||
isPredicated(--I) || !isTerminatorInstr(I->getOpcode())) { isPredicated(--I) || !isUnpredicatedTerminator(I)) {
if (LastOpc == ARM::B || LastOpc == ARM::tB) { if (LastOpc == ARM::B || LastOpc == ARM::tB) {
TBB = LastInst->getOperand(0).getMachineBasicBlock(); TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false; return false;
@ -332,7 +332,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there are three terminators, we don't know what sort of block this is. // If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && if (SecondLastInst && I != MBB.begin() &&
!isPredicated(--I) && isTerminatorInstr(I->getOpcode())) !isPredicated(--I) && isUnpredicatedTerminator(I))
return true; return true;
// If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it. // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.

6
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -158,14 +158,14 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
std::vector<MachineOperand> &Cond) const { std::vector<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
return false; return false;
// Get the last instruction in the block. // Get the last instruction in the block.
MachineInstr *LastInst = I; MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it. // If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastInst->getOpcode() == Alpha::BR) { if (LastInst->getOpcode() == Alpha::BR) {
TBB = LastInst->getOperand(0).getMachineBasicBlock(); TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false; return false;
@ -186,7 +186,7 @@ bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TB
// If there are three terminators, we don't know what sort of block this is. // If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && if (SecondLastInst && I != MBB.begin() &&
isTerminatorInstr((--I)->getOpcode())) isUnpredicatedTerminator(--I))
return true; return true;
// If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it. // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.

6
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -180,14 +180,14 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
std::vector<MachineOperand> &Cond) const { std::vector<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
return false; return false;
// Get the last instruction in the block. // Get the last instruction in the block.
MachineInstr *LastInst = I; MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it. // If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastInst->getOpcode() == PPC::B) { if (LastInst->getOpcode() == PPC::B) {
TBB = LastInst->getOperand(0).getMachineBasicBlock(); TBB = LastInst->getOperand(0).getMachineBasicBlock();
return false; return false;
@ -207,7 +207,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// If there are three terminators, we don't know what sort of block this is. // If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && if (SecondLastInst && I != MBB.begin() &&
isTerminatorInstr((--I)->getOpcode())) isUnpredicatedTerminator(--I))
return true; return true;
// If the block ends with PPC::B and PPC:BCC, handle it. // If the block ends with PPC::B and PPC:BCC, handle it.

7
lib/Target/TargetInstrInfo.cpp
View File

@ -84,3 +84,10 @@ bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
} }
return MadeChange; return MadeChange;
} }
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
if (TID->Flags & M_TERMINATOR_FLAG)
return !isPredicated(MI);
return false;
}

4
lib/Target/X86/X86InstrInfo.cpp
View File

@ -382,14 +382,14 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
return false; return false;
// Get the last instruction in the block. // Get the last instruction in the block.
MachineInstr *LastInst = I; MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it. // If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (!isBranch(LastInst->getOpcode())) if (!isBranch(LastInst->getOpcode()))
return true; return true;