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Modified some assert() msg strings; no other functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102008 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2010-04-21 18:37:48 +00:00
parent 00207237dd
commit c048f1d12c
1 changed files with 14 additions and 14 deletions
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28
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@@ -624,7 +624,7 @@ static bool DisassembleThumb1LdStSP(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert((Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) assert((Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
&& "Invalid opcode"); && "Unexpected opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false; if (!OpInfo) return false;
@@ -652,7 +652,7 @@ static bool DisassembleThumb1LdStSP(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert(Opcode == ARM::tADDrPCi && "Invalid opcode"); assert(Opcode == ARM::tADDrPCi && "Unexpected opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false; if (!OpInfo) return false;
@@ -677,7 +677,7 @@ static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert(Opcode == ARM::tADDrSPi && "Invalid opcode"); assert(Opcode == ARM::tADDrSPi && "Unexpected opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
if (!OpInfo) return false; if (!OpInfo) return false;
@@ -708,7 +708,7 @@ static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert((Opcode == ARM::tPUSH || Opcode == ARM::tPOP) && "Invalid opcode"); assert((Opcode == ARM::tPUSH || Opcode == ARM::tPOP) && "Unexpected opcode");
unsigned &OpIdx = NumOpsAdded; unsigned &OpIdx = NumOpsAdded;
@@ -821,7 +821,7 @@ static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
getT1tRn(insn)))); getT1tRn(insn))));
} else { } else {
// CBNZ, CBZ // CBNZ, CBZ
assert((Opcode == ARM::tCBNZ || Opcode == ARM::tCBZ) && "Invalid opcode"); assert((Opcode == ARM::tCBNZ || Opcode == ARM::tCBZ) &&"Unexpected opcode");
MI.addOperand(MCOperand::CreateImm(getT1Imm6(insn) * 2)); MI.addOperand(MCOperand::CreateImm(getT1Imm6(insn) * 2));
} }
@@ -839,7 +839,7 @@ static bool DisassembleThumb1LdStMul(bool Ld, MCInst &MI, unsigned Opcode,
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert((Opcode == ARM::tLDM || Opcode == ARM::tLDM_UPD || assert((Opcode == ARM::tLDM || Opcode == ARM::tLDM_UPD ||
Opcode == ARM::tSTM_UPD) && "Invalid opcode"); Opcode == ARM::tSTM_UPD) && "Unexpected opcode");
unsigned &OpIdx = NumOpsAdded; unsigned &OpIdx = NumOpsAdded;
@@ -1123,7 +1123,7 @@ static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
assert((Opcode == ARM::t2LDM || Opcode == ARM::t2LDM_UPD || assert((Opcode == ARM::t2LDM || Opcode == ARM::t2LDM_UPD ||
Opcode == ARM::t2STM || Opcode == ARM::t2STM_UPD) Opcode == ARM::t2STM || Opcode == ARM::t2STM_UPD)
&& "Invalid opcode"); && "Unexpected opcode");
assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5"); assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
unsigned &OpIdx = NumOpsAdded; unsigned &OpIdx = NumOpsAdded;
@@ -1363,7 +1363,7 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRn(insn)))); decodeRn(insn))));
++OpIdx; ++OpIdx;
} else { } else {
DEBUG(errs() << "Thumb encoding error: d==15 for three-reg operands.\n"); DEBUG(errs() << "Thumb2 encoding error: d==15 for three-reg operands.\n");
return false; return false;
} }
} }
@@ -1431,7 +1431,7 @@ static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
if (TwoReg) { if (TwoReg) {
if (NoDstReg) { if (NoDstReg) {
DEBUG(errs() << "Thumb encoding error: d==15 for DPModImm 2-reg instr.\n"); DEBUG(errs()<<"Thumb2 encoding error: d==15 for DPModImm 2-reg instr.\n");
return false; return false;
} }
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
@@ -1476,7 +1476,7 @@ static inline unsigned decodeThumb2SaturatePos(unsigned Opcode, uint32_t insn) {
case ARM::t2USAT16: case ARM::t2USAT16:
return slice(insn, 3, 0); return slice(insn, 3, 0);
default: default:
assert(0 && "Invalid opcode passed in"); assert(0 && "Unexpected opcode");
return 0; return 0;
} }
} }
@@ -1576,7 +1576,7 @@ static bool DisassembleThumb2DPBinImm(MCInst &MI, unsigned Opcode,
} else { } else {
// Handle the case of: lsb width // Handle the case of: lsb width
assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX || assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX ||
Opcode == ARM::t2BFI) && "Invalid opcode"); Opcode == ARM::t2BFI) && "Unexpected opcode");
MI.addOperand(MCOperand::CreateImm(getLsb(insn))); MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
if (Opcode == ARM::t2BFI) { if (Opcode == ARM::t2BFI) {
if (getMsb(insn) < getLsb(insn)) { if (getMsb(insn) < getLsb(insn)) {
@@ -1705,7 +1705,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
switch (Opcode) { switch (Opcode) {
default: default:
assert(0 && "Unreachable code"); assert(0 && "Unexpected opcode");
return false; return false;
case ARM::t2B: case ARM::t2B:
Offset = decodeImm32_B_EncodingT4(insn); Offset = decodeImm32_B_EncodingT4(insn);
@@ -2122,7 +2122,7 @@ static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
} }
// Load/store dual, load/store exclusive, table branch, otherwise. // Load/store dual, load/store exclusive, table branch, otherwise.
assert(slice(op2, 2, 2) == 1 && "Encoding error"); assert(slice(op2, 2, 2) == 1 && "Thumb2 encoding error!");
if ((ARM::t2LDREX <= Opcode && Opcode <= ARM::t2LDREXH) || if ((ARM::t2LDREX <= Opcode && Opcode <= ARM::t2LDREXH) ||
(ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH)) { (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH)) {
// Load/store exclusive. // Load/store exclusive.
@@ -2209,7 +2209,7 @@ static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
break; break;
default: default:
assert(0 && "Encoding error for Thumb2 instruction!"); assert(0 && "Thumb2 encoding error!");
break; break;
} }