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R600/SI: Add missing SOPK instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2015-04-08 01:09:22 +00:00
parent 434e097df8
commit c0578c36bb
3 changed files with 72 additions and 13 deletions
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13
lib/Target/R600/SIInstrFormats.td
View File

@ -181,6 +181,19 @@ class SOPKe <bits<5> op> : Enc32 {
let Inst{31-28} = 0xb; //encoding
}
class SOPK64e <bits<5> op> : Enc64 {
bits <7> sdst = 0;
bits <16> simm16;
bits <32> imm;
let Inst{15-0} = simm16;
let Inst{22-16} = sdst;
let Inst{27-23} = op;
let Inst{31-28} = 0xb;
let Inst{63-32} = imm;
}
class SOPPe <bits<7> op> : Enc32 {
bits <16> simm16;

44
lib/Target/R600/SIInstrInfo.td
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@ -547,6 +547,16 @@ class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
SOPKe <op.VI>,
SIMCInstr<opName, SISubtarget.VI>;
multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
string asm = opName#opAsm> {
def "" : SOPK_Pseudo <opName, outs, ins, []>;
def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
}
multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
pattern>;
@ -562,13 +572,39 @@ multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
(ins SReg_32:$src0, u16imm:$src1), pattern>;
def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
let DisableEncoding = "$dst" in {
def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$src0, u16imm:$src1), opName#" $dst, $src0">;
def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
}
}
multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
" $sdst, $simm16"
>;
multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
string argAsm, string asm = opName#argAsm> {
def "" : SOPK_Pseudo <opName, outs, ins, []>;
def _si : SOPK <outs, ins, asm, []>,
SOPK64e <op.SI>,
SIMCInstr<opName, SISubtarget.SI> {
let AssemblerPredicates = [isSICI];
let isCodeGenOnly = 0;
}
def _vi : SOPK <outs, ins, asm, []>,
SOPK64e <op.VI>,
SIMCInstr<opName, SISubtarget.VI> {
let AssemblerPredicates = [isVI];
let isCodeGenOnly = 0;
}
}
//===----------------------------------------------------------------------===//
// SMRD classes
//===----------------------------------------------------------------------===//

28
lib/Target/R600/SIInstructions.td
View File

@ -387,6 +387,7 @@ defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32",
>;
*/
defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>;
defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>;
defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>;
defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>;
@ -400,18 +401,27 @@ defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>;
defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>;
} // End isCompare = 1
let isCommutable = 1 in {
let Defs = [SCC], isCommutable = 1 in {
defm S_ADDK_I32 : SOPK_32 <sopk<0x0f, 0x0e>, "s_addk_i32", []>;
}
defm S_MULK_I32 : SOPK_32 <sopk<0x10, 0x0f>, "s_mulk_i32", []>;
let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
Constraints = "$sdst = $src0" in {
defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>;
defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>;
}
//defm S_CBRANCH_I_FORK : SOPK_ <sopk<0x11, 0x10>, "s_cbranch_i_fork", []>;
defm S_CBRANCH_I_FORK : SOPK_m <
sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs),
(ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
>;
defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>;
defm S_SETREG_B32 : SOPK_32 <sopk<0x13, 0x12>, "s_setreg_b32", []>;
defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
//defm S_SETREG_IMM32_B32 : SOPK_32 <sopk<0x15, 0x14>, "s_setreg_imm32_b32", []>;
defm S_SETREG_B32 : SOPK_m <
sopk<0x13, 0x12>, "s_setreg_b32", (outs),
(ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"
>;
// FIXME: Not on SI?
//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
(ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16"
>;
//===----------------------------------------------------------------------===//
// SOPP Instructions