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Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-07 00:24:52 +00:00
parent 271cc67044
commit c10b5afbe8
2 changed files with 23 additions and 32 deletions
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32
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -723,6 +723,18 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
return true;
}
static const
MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
unsigned Reg, unsigned SubIdx, unsigned State,
const TargetRegisterInfo *TRI) {
if (!SubIdx)
return MIB.addReg(Reg, State);
if (TargetRegisterInfo::isPhysicalRegister(Reg))
return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
return MIB.addReg(Reg, State, SubIdx);
}
void ARMBaseInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
@ -764,13 +776,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_8RegisterClass) {
// FIXME: Neon instructions should support predicates
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
.addFrameIndex(FI).addImm(128)
.addMemOperand(MMO)
.addReg(SrcReg, getKillRegState(isKill)));
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI).addImm(128);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
AddDefaultPred(MIB.addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)).
addReg(SrcReg, getKillRegState(isKill))
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
.addMemOperand(MMO));
@ -820,9 +833,10 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_VFP2RegisterClass ||
RC == ARM::QPR_8RegisterClass) {
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
.addFrameIndex(FI).addImm(128)
.addMemOperand(MMO));
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1q64));
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
.addFrameIndex(FI)

23
lib/Target/ARM/ARMInstrNEON.td
View File

@ -128,17 +128,6 @@ def VLDMQ_UPD
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}!, ${dst:dregpair}",
"$addr.base = $wb", []>;
// Use vld1 to load a Q register as a D register pair.
// This alternative to VLDMQ allows an alignment to be specified.
// This is equivalent to VLD1q64 except that it has a Q register operand.
def VLD1q
: NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst), (ins addrmode6:$addr),
IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
def VLD1q_UPD
: NLdSt<0,0b10,0b1010,0b1100, (outs QPR:$dst, GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", "64",
"${dst:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
} // mayLoad = 1
let mayStore = 1 in {
@ -154,18 +143,6 @@ def VSTMQ_UPD
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}!, ${src:dregpair}",
"$addr.base = $wb", []>;
// Use vst1 to store a Q register as a D register pair.
// This alternative to VSTMQ allows an alignment to be specified.
// This is equivalent to VST1q64 except that it has a Q register operand.
def VST1q
: NLdSt<0,0b00,0b1010,0b1100, (outs), (ins addrmode6:$addr, QPR:$src),
IIC_VST, "vst1", "64", "${src:dregpair}, $addr", "", []>;
def VST1q_UPD
: NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset, QPR:$src),
IIC_VST, "vst1", "64", "{$src:dregpair}, $addr$offset",
"$addr.addr = $wb", []>;
} // mayStore = 1
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {