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Apply a patch by Micah Villmow to fix AsmParser to accept vector
shift constant expressions, and add support for folding vector shift constant expressions. This fixes PR3802. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67010 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -832,6 +832,12 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode,
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return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getOr);
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case Instruction::Xor:
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return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getXor);
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case Instruction::LShr:
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return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getLShr);
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case Instruction::AShr:
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return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getAShr);
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case Instruction::Shl:
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return EvalVectorOp(CP1, CP2, VTy, ConstantExpr::getShl);
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}
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}
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}
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@ -2095,7 +2095,7 @@ Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) {
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case Instruction::LShr:
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case Instruction::AShr:
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assert(C1->getType() == C2->getType() && "Op types should be identical!");
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assert(C1->getType()->isInteger() &&
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assert(C1->getType()->isIntOrIntVector() &&
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"Tried to create a shift operation on a non-integer type!");
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break;
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default:
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@ -1,6 +1,6 @@
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep shl
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep ashr
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep lshr
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep shl | count 1
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep ashr | count 1
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; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | grep lshr | count 1
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define <4 x i32> @foo(<4 x i32> %a, <4 x i32> %b) nounwind {
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entry:
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@ -19,3 +19,14 @@ entry:
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%cmp = ashr <4 x i32> %a, %b ; <4 x i32> [#uses=1]
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ret <4 x i32> %cmp
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}
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; Constant expressions: these should be folded.
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define <2 x i64> @foo_ce() nounwind {
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ret <2 x i64> shl (<2 x i64> <i64 5, i64 6>, <2 x i64> <i64 3, i64 5>)
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}
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define <2 x i64> @bar_ce() nounwind {
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ret <2 x i64> lshr (<2 x i64> <i64 340, i64 380>, <2 x i64> <i64 3, i64 5>)
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}
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define <2 x i64> @baz_ce() nounwind {
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ret <2 x i64> ashr (<2 x i64> <i64 573, i64 411>, <2 x i64> <i64 3, i64 5>)
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}
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