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Fix my brain cramp by inverting the assertion condition.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76131 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-07-17 00:32:06 +00:00
parent 28ebfcf7de
commit c1b46f91f5
1 changed files with 1 additions and 3 deletions
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4
lib/CodeGen/VirtRegRewriter.cpp
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@@ -491,12 +491,10 @@ static void ReMaterialize(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
VirtRegMap &VRM) { VirtRegMap &VRM) {
MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
#if 0
#ifndef NDEBUG #ifndef NDEBUG
const TargetInstrDesc &TID = ReMatDefMI->getDesc(); const TargetInstrDesc &TID = ReMatDefMI->getDesc();
assert(TID.getNumDefs() != 1 && assert(TID.getNumDefs() == 1 &&
"Don't know how to remat instructions that define > 1 values!"); "Don't know how to remat instructions that define > 1 values!");
#endif
#endif #endif
TII->reMaterialize(MBB, MII, DestReg, TII->reMaterialize(MBB, MII, DestReg,
ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI); ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);