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[Hexagon] Adding aslh instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-11-24 17:44:19 +00:00
parent f309d8ee65
commit c1c7be0928
3 changed files with 17 additions and 5 deletions
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8
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -713,7 +713,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::ADD_ri: case Hexagon::ADD_ri:
return isInt<8>(MI->getOperand(2).getImm()); return isInt<8>(MI->getOperand(2).getImm());
case Hexagon::ASLH: case Hexagon::A2_aslh:
case Hexagon::ASRH: case Hexagon::ASRH:
case Hexagon::A2_sxtb: case Hexagon::A2_sxtb:
case Hexagon::A2_sxth: case Hexagon::A2_sxth:
@ -1303,6 +1303,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A2_pandfnew: case Hexagon::A2_pandfnew:
case Hexagon::A2_pandt: case Hexagon::A2_pandt:
case Hexagon::A2_pandtnew: case Hexagon::A2_pandtnew:
case Hexagon::A4_paslhf:
case Hexagon::A4_paslhfnew:
case Hexagon::A4_paslht:
case Hexagon::A4_paslhtnew:
case Hexagon::A2_porf: case Hexagon::A2_porf:
case Hexagon::A2_porfnew: case Hexagon::A2_porfnew:
case Hexagon::A2_port: case Hexagon::A2_port:
@ -1336,8 +1340,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::COMBINE_rr_cPt: case Hexagon::COMBINE_rr_cPt:
case Hexagon::COMBINE_rr_cNotPt: case Hexagon::COMBINE_rr_cNotPt:
return true; return true;
case Hexagon::ASLH_cPt_V4:
case Hexagon::ASLH_cNotPt_V4:
case Hexagon::ASRH_cPt_V4: case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4: case Hexagon::ASRH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps(); return QRI.Subtarget.hasV4TOps();

4
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -265,6 +265,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
} }
} }
defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
@ -634,11 +635,10 @@ multiclass ALU32_2op_base2<string mnemonic> {
} }
} }
defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel;
defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel; defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
def : Pat <(shl (i32 IntRegs:$src1), (i32 16)), def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
(ASLH IntRegs:$src1)>; (A2_aslh IntRegs:$src1)>;
def : Pat <(sra (i32 IntRegs:$src1), (i32 16)), def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
(ASRH IntRegs:$src1)>; (ASRH IntRegs:$src1)>;

10
test/MC/Hexagon/inst_aslh.ll Normal file
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@ -0,0 +1,10 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
define i32 @foo (i32 %a)
{
%1 = shl i32 %a, 16
ret i32 %1
}
; CHECK: 0000 00400070 00c09f52