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Don't cache the instruction and register info from the TargetMachine, because

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the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-06-07 20:35:25 +00:00
parent 8b0f77bb96
commit c1dcb8d654
4 changed files with 10 additions and 9 deletions
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8
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -39,11 +39,10 @@ namespace {
/// layout, etc.
///
TargetMachine &TM;
const TargetInstrInfo *TII;
static char ID;
Filler(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
: MachineFunctionPass(ID), TM(tm) { }
virtual const char *getPassName() const {
return "SPARC Delay Slot Filler";
@ -127,6 +126,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
++FilledSlots;
Changed = true;
const TargetInstrInfo *TII = TM.getInstrInfo();
if (D == MBB.end())
BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
else
@ -166,7 +166,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB,
if (J->getOpcode() == SP::RESTORErr
|| J->getOpcode() == SP::RESTOREri) {
// change retl to ret.
slot->setDesc(TII->get(SP::RET));
slot->setDesc(TM.getInstrInfo()->get(SP::RET));
return J;
}
}
@ -476,6 +476,8 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
if (isDelayFiller(MBB, PrevInst))
return false;
const TargetInstrInfo *TII = TM.getInstrInfo();
switch (PrevInst->getOpcode()) {
default: break;
case SP::ADDrr:

2
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -29,7 +29,7 @@ using namespace llvm;
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
: SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
RI(ST, *this), Subtarget(ST) {
RI(ST), Subtarget(ST) {
}
/// isLoadFromStackSlot - If the specified machine instruction is a direct

6
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -34,9 +34,8 @@ static cl::opt<bool>
ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
cl::desc("Reserve application registers (%g2-%g4)"));
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
const TargetInstrInfo &tii)
: SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
: SparcGenRegisterInfo(SP::I7), Subtarget(st) {
}
const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
@ -108,6 +107,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
unsigned OffHi = (unsigned)Offset >> 10U;
BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6

3
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -27,9 +27,8 @@ class Type;
struct SparcRegisterInfo : public SparcGenRegisterInfo {
SparcSubtarget &Subtarget;
const TargetInstrInfo &TII;
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
SparcRegisterInfo(SparcSubtarget &st);
/// Code Generation virtual methods...
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;