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ms inline asm: Don't add x86 segment registers to the clobber list.

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Clang tries to check the clobber list but doesn't list segment registers in its
x86 register list. This fixes PR20343.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nico Weber 2014-07-17 20:24:55 +00:00
parent 822f1b191a
commit c1ef24ce39
3 changed files with 10 additions and 1 deletions
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3
include/llvm/MC/MCTargetAsmParser.h
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@ -164,6 +164,9 @@ public:
unsigned &ErrorInfo, unsigned &ErrorInfo,
bool MatchingInlineAsm) = 0; bool MatchingInlineAsm) = 0;
/// Allows targets to let registers opt out of clobber lists.
virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
/// Allow a target to add special case operand matching for things that /// Allow a target to add special case operand matching for things that
/// tblgen doesn't/can't handle effectively. For example, literal /// tblgen doesn't/can't handle effectively. For example, literal
/// immediates on ARM. TableGen expects a token operand, but the parser /// immediates on ARM. TableGen expects a token operand, but the parser

3
lib/MC/MCParser/AsmParser.cpp
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@ -4510,7 +4510,8 @@ bool AsmParser::parseMSInlineAsm(
continue; continue;
// Register operand. // Register operand.
if (Operand.isReg() && !Operand.needAddressOf()) { if (Operand.isReg() && !Operand.needAddressOf() &&
!getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs(); unsigned NumDefs = Desc.getNumDefs();
// Clobber. // Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs) if (NumDefs && Operand.getMCOperandNum() < NumDefs)

5
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -696,6 +696,8 @@ private:
unsigned &ErrorInfo, unsigned &ErrorInfo,
bool MatchingInlineAsm) override; bool MatchingInlineAsm) override;
virtual bool OmitRegisterFromClobberLists(unsigned RegNo) override;
/// doSrcDstMatch - Returns true if operands are matching in their /// doSrcDstMatch - Returns true if operands are matching in their
/// word size (%si and %di, %esi and %edi, etc.). Order depends on /// word size (%si and %di, %esi and %edi, etc.). Order depends on
/// the parsing mode (Intel vs. AT&T). /// the parsing mode (Intel vs. AT&T).
@ -2520,6 +2522,9 @@ bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return true; return true;
} }
bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
}
bool X86AsmParser::ParseDirective(AsmToken DirectiveID) { bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier(); StringRef IDVal = DirectiveID.getIdentifier();