From c1fb0473ed415824bf6ffdbd8d6e3c4a31db3d62 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Sat, 10 Mar 2007 09:57:05 +0000 Subject: [PATCH] Adding more arithmetic operators to MMX. This is an almost exact copy of the addition. Please let me know if you have suggestions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IntrinsicsX86.td | 16 ++++++ lib/Target/X86/X86ISelLowering.cpp | 4 ++ lib/Target/X86/X86InstrMMX.td | 10 ++++ test/CodeGen/X86/mmx-arith.ll | 79 ++++++++++++++++++++++++------ 4 files changed, 94 insertions(+), 15 deletions(-) diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index 76db55ab294..48aa1a7120c 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -547,6 +547,7 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". // Integer arithmetic ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + // Addition def int_x86_mmx_padds_b : GCCBuiltin<"__builtin_ia32_paddsb">, Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; @@ -560,4 +561,19 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem]>; + + // Subtraction + def int_x86_mmx_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb">, + Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + llvm_v8i8_ty], [IntrNoMem]>; + def int_x86_mmx_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw">, + Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_v4i16_ty], [IntrNoMem]>; + + def int_x86_mmx_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb">, + Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty, + llvm_v8i8_ty], [IntrNoMem]>; + def int_x86_mmx_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw">, + Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_v4i16_ty], [IntrNoMem]>; } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2ab5e086197..4fecb70cd29 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -331,6 +331,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::ADD, MVT::v4i16, Legal); setOperationAction(ISD::ADD, MVT::v2i32, Legal); + setOperationAction(ISD::SUB, MVT::v8i8, Legal); + setOperationAction(ISD::SUB, MVT::v4i16, Legal); + setOperationAction(ISD::SUB, MVT::v2i32, Legal); + setOperationAction(ISD::LOAD, MVT::v8i8, Promote); AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32); setOperationAction(ISD::LOAD, MVT::v4i16, Promote); diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 5096c203bac..73f2f11a863 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -101,6 +101,16 @@ defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>; defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>; defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>; +defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>; +defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>; +defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>; + +defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>; +defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>; + +defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>; +defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>; + // Move Instructions def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", []>; diff --git a/test/CodeGen/X86/mmx-arith.ll b/test/CodeGen/X86/mmx-arith.ll index 3911be60b3d..7c71cfc9f1f 100644 --- a/test/CodeGen/X86/mmx-arith.ll +++ b/test/CodeGen/X86/mmx-arith.ll @@ -2,34 +2,83 @@ ;; A basic sanity check to make sure that MMX arithmetic actually compiles. -define void @foo(<2 x i32>* %A, <2 x i32>* %B) { +define void @foo(<8 x i8>* %A, <8 x i8>* %B) { +entry: + %tmp5 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1] + %tmp7 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1] + %tmp8 = add <8 x i8> %tmp5, %tmp7 ; <<8 x i8>> [#uses=2] + store <8 x i8> %tmp8, <8 x i8>* %A + %tmp14 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1] + %tmp25 = tail call <8 x i8> @llvm.x86.mmx.padds.b( <8 x i8> %tmp14, <8 x i8> %tmp8 ) ; <<8 x i8>> [#uses=2] + store <8 x i8> %tmp25, <8 x i8>* %B + %tmp36 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1] + %tmp49 = tail call <8 x i8> @llvm.x86.mmx.paddus.b( <8 x i8> %tmp36, <8 x i8> %tmp25 ) ; <<8 x i8>> [#uses=2] + store <8 x i8> %tmp49, <8 x i8>* %B + %tmp58 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1] + %tmp61 = sub <8 x i8> %tmp58, %tmp49 ; <<8 x i8>> [#uses=2] + store <8 x i8> %tmp61, <8 x i8>* %B + %tmp64 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1] + %tmp80 = tail call <8 x i8> @llvm.x86.mmx.psubs.b( <8 x i8> %tmp61, <8 x i8> %tmp64 ) ; <<8 x i8>> [#uses=2] + store <8 x i8> %tmp80, <8 x i8>* %A + %tmp89 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1] + %tmp105 = tail call <8 x i8> @llvm.x86.mmx.psubus.b( <8 x i8> %tmp80, <8 x i8> %tmp89 ) ; <<8 x i8>> [#uses=1] + store <8 x i8> %tmp105, <8 x i8>* %A + tail call void @llvm.x86.mmx.emms( ) + ret void +} + +define void @baz(<2 x i32>* %A, <2 x i32>* %B) { entry: %tmp1 = load <2 x i32>* %A ; <<2 x i32>> [#uses=1] %tmp3 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1] - %tmp4 = add <2 x i32> %tmp1, %tmp3 ; <<2 x i32>> [#uses=1] + %tmp4 = add <2 x i32> %tmp1, %tmp3 ; <<2 x i32>> [#uses=2] store <2 x i32> %tmp4, <2 x i32>* %A + %tmp9 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1] + %tmp10 = sub <2 x i32> %tmp4, %tmp9 ; <<2 x i32>> [#uses=1] + store <2 x i32> %tmp10, <2 x i32>* %B tail call void @llvm.x86.mmx.emms( ) ret void } define void @bar(<4 x i16>* %A, <4 x i16>* %B) { entry: - %tmp1 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1] - %tmp3 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1] - %tmp4 = add <4 x i16> %tmp1, %tmp3 ; <<4 x i16>> [#uses=1] - store <4 x i16> %tmp4, <4 x i16>* %A + %tmp5 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1] + %tmp7 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1] + %tmp8 = add <4 x i16> %tmp5, %tmp7 ; <<4 x i16>> [#uses=2] + store <4 x i16> %tmp8, <4 x i16>* %A + %tmp14 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1] + %tmp25 = tail call <4 x i16> @llvm.x86.mmx.padds.w( <4 x i16> %tmp14, <4 x i16> %tmp8 ) ; <<4 x i16>> [#uses=2] + store <4 x i16> %tmp25, <4 x i16>* %B + %tmp36 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1] + %tmp49 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp36, <4 x i16> %tmp25 ) ; <<4 x i16>> [#uses=2] + store <4 x i16> %tmp49, <4 x i16>* %B + %tmp58 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1] + %tmp61 = sub <4 x i16> %tmp58, %tmp49 ; <<4 x i16>> [#uses=2] + store <4 x i16> %tmp61, <4 x i16>* %B + %tmp64 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1] + %tmp80 = tail call <4 x i16> @llvm.x86.mmx.psubs.w( <4 x i16> %tmp61, <4 x i16> %tmp64 ) ; <<4 x i16>> [#uses=2] + store <4 x i16> %tmp80, <4 x i16>* %A + %tmp89 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1] + %tmp105 = tail call <4 x i16> @llvm.x86.mmx.psubus.w( <4 x i16> %tmp80, <4 x i16> %tmp89 ) ; <<4 x i16>> [#uses=1] + store <4 x i16> %tmp105, <4 x i16>* %A tail call void @llvm.x86.mmx.emms( ) ret void } -define void @baz(<8 x i8>* %A, <8 x i8>* %B) { -entry: - %tmp1 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1] - %tmp3 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1] - %tmp4 = add <8 x i8> %tmp1, %tmp3 ; <<8 x i8>> [#uses=1] - store <8 x i8> %tmp4, <8 x i8>* %A - tail call void @llvm.x86.mmx.emms( ) - ret void -} +declare <4 x i16> @llvm.x86.mmx.padds.w(<4 x i16>, <4 x i16>) + +declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>) + +declare <4 x i16> @llvm.x86.mmx.psubs.w(<4 x i16>, <4 x i16>) + +declare <4 x i16> @llvm.x86.mmx.psubus.w(<4 x i16>, <4 x i16>) + +declare <8 x i8> @llvm.x86.mmx.padds.b(<8 x i8>, <8 x i8>) + +declare <8 x i8> @llvm.x86.mmx.paddus.b(<8 x i8>, <8 x i8>) + +declare <8 x i8> @llvm.x86.mmx.psubs.b(<8 x i8>, <8 x i8>) + +declare <8 x i8> @llvm.x86.mmx.psubus.b(<8 x i8>, <8 x i8>) declare void @llvm.x86.mmx.emms()