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Simplify code, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakub Staszak 2012-12-29 15:57:26 +00:00
parent 3c0307d760
commit c20323a758
1 changed files with 14 additions and 19 deletions
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33
lib/Target/X86/X86ISelLowering.cpp
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@ -1733,7 +1733,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CCInfo.AnalyzeCallResult(Ins, RetCC_X86); CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
// Copy all of the result registers out of their specified physreg. // Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) { for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
CCValAssign &VA = RVLocs[i]; CCValAssign &VA = RVLocs[i];
EVT CopyVT = VA.getValVT(); EVT CopyVT = VA.getValVT();
@ -1990,10 +1990,9 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
if (VA.isExtInLoc()) { if (VA.isExtInLoc()) {
// Handle MMX values passed in XMM regs. // Handle MMX values passed in XMM regs.
if (RegVT.isVector()) { if (RegVT.isVector())
ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
ArgValue); else
} else
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
} }
} else { } else {
@ -12405,18 +12404,16 @@ bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
return false; return false;
unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
if (NumBits1 <= NumBits2) return NumBits1 > NumBits2;
return false;
return true;
} }
bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const { bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
return Imm == (int32_t)Imm; return isInt<32>(Imm);
} }
bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const { bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
// Can also use sub to handle negated immediates. // Can also use sub to handle negated immediates.
return Imm == (int32_t)Imm; return isInt<32>(Imm);
} }
bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
@ -12424,9 +12421,7 @@ bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
return false; return false;
unsigned NumBits1 = VT1.getSizeInBits(); unsigned NumBits1 = VT1.getSizeInBits();
unsigned NumBits2 = VT2.getSizeInBits(); unsigned NumBits2 = VT2.getSizeInBits();
if (NumBits1 <= NumBits2) return NumBits1 > NumBits2;
return false;
return true;
} }
bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
@ -17553,13 +17548,13 @@ TargetLowering::ConstraintWeight
case 'f': case 'f':
case 't': case 't':
case 'u': case 'u':
if (type->isFloatingPointTy()) if (type->isFloatingPointTy())
weight = CW_SpecificReg; weight = CW_SpecificReg;
break; break;
case 'y': case 'y':
if (type->isX86_MMXTy() && Subtarget->hasMMX()) if (type->isX86_MMXTy() && Subtarget->hasMMX())
weight = CW_SpecificReg; weight = CW_SpecificReg;
break; break;
case 'x': case 'x':
case 'Y': case 'Y':
if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) || if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||