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[mips] Refactor unconditional branch instruction. Separate encoding information
from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170663 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -279,6 +279,17 @@ class BGEZ_FM<bits<6> op, bits<5> funct> {
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let Inst{15-0} = offset;
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}
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class B_FM {
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = 4;
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let Inst{25-21} = 0;
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let Inst{20-16} = 0;
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let Inst{15-0} = offset;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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@ -596,11 +596,9 @@ class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
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}
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// Unconditional branch
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class UncondBranch<bits<6> op, string instr_asm>:
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BranchBase<op, (outs), (ins brtarget:$imm16),
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!strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
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let rs = 0;
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let rt = 0;
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class UncondBranch<string opstr> :
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InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
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[(br bb:$offset)], IIBranch, FrmI> {
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let isBranch = 1;
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let isTerminator = 1;
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let isBarrier = 1;
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@ -979,7 +977,7 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
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def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
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Requires<[RelocStatic, HasStdEnc]>, IsBranch;
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def JR : IndirectBranch<CPURegs>;
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def B : UncondBranch<0x04, "b">;
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def B : UncondBranch<"b">, B_FM;
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def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
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def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
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def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
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