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The Thumb tADDrSPi instruction is not valid when the destination is SP.
Check for that and try narrowing it to tADDspi instead. Radar 8724703. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,7 +58,7 @@ namespace {
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{ ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
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{ ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
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// Note: immediate scale is 4.
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{ ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0 },
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{ ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 1 },
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{ ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
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{ ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
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{ ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
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@ -469,6 +469,13 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
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return true;
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
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}
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case ARM::t2ADDrSPi: {
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static const ReduceEntry NarrowEntry =
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{ ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 1 };
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if (MI->getOperand(0).getReg() == ARM::SP)
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return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR);
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return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
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}
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}
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return false;
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}
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11
test/CodeGen/Thumb2/2010-12-03-AddSPNarrowing.ll
Normal file
11
test/CodeGen/Thumb2/2010-12-03-AddSPNarrowing.ll
Normal file
@ -0,0 +1,11 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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; Radar 8724703: Make sure that a t2ADDrSPi instruction with SP as the
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; destination register is narrowed to tADDspi instead of tADDrSPi.
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define void @test() nounwind {
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entry:
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; CHECK: sub.w
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; CHECK: add.w
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%Buffer.i = alloca [512 x i8], align 4
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ret void
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}
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