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https://github.com/c64scene-ar/llvm-6502.git
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Reduce indentation via early exit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
0dd4558e7d
commit
c25ccf85e5
@ -6026,6 +6026,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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bool NeedCF = false;
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bool NeedOF = false;
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switch (X86CC) {
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default: break;
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case X86::COND_A: case X86::COND_AE:
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case X86::COND_B: case X86::COND_BE:
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NeedCF = true;
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@ -6035,120 +6036,129 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
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case X86::COND_O: case X86::COND_NO:
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NeedOF = true;
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break;
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default: break;
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}
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// See if we can use the EFLAGS value from the operand instead of
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// doing a separate TEST. TEST always sets OF and CF to 0, so unless
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// we prove that the arithmetic won't overflow, we can't use OF or CF.
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if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
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unsigned Opcode = 0;
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unsigned NumOperands = 0;
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switch (Op.getNode()->getOpcode()) {
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case ISD::ADD:
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// Due to an isel shortcoming, be conservative if this add is
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// likely to be selected as part of a load-modify-store
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// instruction. When the root node in a match is a store, isel
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// doesn't know how to remap non-chain non-flag uses of other
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// nodes in the match, such as the ADD in this case. This leads
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// to the ADD being left around and reselected, with the result
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// being two adds in the output. Alas, even if none our users
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// are stores, that doesn't prove we're O.K. Ergo, if we have
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// any parents that aren't CopyToReg or SETCC, eschew INC/DEC.
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// A better fix seems to require climbing the DAG back to the
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// root, and it doesn't seem to be worth the effort.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
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goto default_case;
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
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// An add of one will be selected as an INC.
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if (C->getAPIntValue() == 1) {
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Opcode = X86ISD::INC;
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NumOperands = 1;
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break;
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}
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// An add of negative one (subtract of one) will be selected as a DEC.
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if (C->getAPIntValue().isAllOnesValue()) {
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Opcode = X86ISD::DEC;
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NumOperands = 1;
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break;
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}
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}
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// Otherwise use a regular EFLAGS-setting add.
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Opcode = X86ISD::ADD;
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NumOperands = 2;
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break;
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case ISD::AND: {
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// If the primary and result isn't used, don't bother using X86ISD::AND,
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// because a TEST instruction will be better.
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bool NonFlagUse = false;
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI) {
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SDNode *User = *UI;
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unsigned UOpNo = UI.getOperandNo();
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if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
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// Look pass truncate.
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UOpNo = User->use_begin().getOperandNo();
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User = *User->use_begin();
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}
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if (User->getOpcode() != ISD::BRCOND &&
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User->getOpcode() != ISD::SETCC &&
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(User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
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NonFlagUse = true;
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break;
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}
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}
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if (!NonFlagUse)
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break;
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}
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// FALL THROUGH
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case ISD::SUB:
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case ISD::OR:
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case ISD::XOR:
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// Due to the ISEL shortcoming noted above, be conservative if this op is
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// likely to be selected as part of a load-modify-store instruction.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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if (Op.getResNo() != 0 || NeedOF || NeedCF)
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// Emit a CMP with 0, which is the TEST pattern.
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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DAG.getConstant(0, Op.getValueType()));
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unsigned Opcode = 0;
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unsigned NumOperands = 0;
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switch (Op.getNode()->getOpcode()) {
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case ISD::ADD:
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// Due to an isel shortcoming, be conservative if this add is likely to be
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// selected as part of a load-modify-store instruction. When the root node
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// in a match is a store, isel doesn't know how to remap non-chain non-flag
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// uses of other nodes in the match, such as the ADD in this case. This
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// leads to the ADD being left around and reselected, with the result being
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// two adds in the output. Alas, even if none our users are stores, that
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// doesn't prove we're O.K. Ergo, if we have any parents that aren't
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// CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
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// climbing the DAG back to the root, and it doesn't seem to be worth the
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// effort.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() == ISD::STORE)
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goto default_case;
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// Otherwise use a regular EFLAGS-setting instruction.
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switch (Op.getNode()->getOpcode()) {
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case ISD::SUB: Opcode = X86ISD::SUB; break;
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case ISD::OR: Opcode = X86ISD::OR; break;
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case ISD::XOR: Opcode = X86ISD::XOR; break;
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case ISD::AND: Opcode = X86ISD::AND; break;
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default: llvm_unreachable("unexpected operator!");
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if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
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goto default_case;
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
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// An add of one will be selected as an INC.
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if (C->getAPIntValue() == 1) {
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Opcode = X86ISD::INC;
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NumOperands = 1;
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break;
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}
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// An add of negative one (subtract of one) will be selected as a DEC.
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if (C->getAPIntValue().isAllOnesValue()) {
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Opcode = X86ISD::DEC;
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NumOperands = 1;
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break;
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}
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NumOperands = 2;
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break;
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case X86ISD::ADD:
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case X86ISD::SUB:
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case X86ISD::INC:
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case X86ISD::DEC:
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case X86ISD::OR:
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case X86ISD::XOR:
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case X86ISD::AND:
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return SDValue(Op.getNode(), 1);
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default:
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default_case:
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break;
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}
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if (Opcode != 0) {
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0; i != NumOperands; ++i)
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Ops.push_back(Op.getOperand(i));
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SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
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DAG.ReplaceAllUsesWith(Op, New);
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return SDValue(New.getNode(), 1);
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// Otherwise use a regular EFLAGS-setting add.
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Opcode = X86ISD::ADD;
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NumOperands = 2;
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break;
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case ISD::AND: {
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// If the primary and result isn't used, don't bother using X86ISD::AND,
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// because a TEST instruction will be better.
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bool NonFlagUse = false;
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI) {
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SDNode *User = *UI;
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unsigned UOpNo = UI.getOperandNo();
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if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
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// Look pass truncate.
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UOpNo = User->use_begin().getOperandNo();
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User = *User->use_begin();
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}
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if (User->getOpcode() != ISD::BRCOND &&
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User->getOpcode() != ISD::SETCC &&
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(User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
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NonFlagUse = true;
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break;
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}
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}
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if (!NonFlagUse)
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break;
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}
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// FALL THROUGH
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case ISD::SUB:
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case ISD::OR:
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case ISD::XOR:
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// Due to the ISEL shortcoming noted above, be conservative if this op is
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// likely to be selected as part of a load-modify-store instruction.
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for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
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UE = Op.getNode()->use_end(); UI != UE; ++UI)
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if (UI->getOpcode() == ISD::STORE)
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goto default_case;
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// Otherwise use a regular EFLAGS-setting instruction.
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switch (Op.getNode()->getOpcode()) {
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default: llvm_unreachable("unexpected operator!");
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case ISD::SUB: Opcode = X86ISD::SUB; break;
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case ISD::OR: Opcode = X86ISD::OR; break;
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case ISD::XOR: Opcode = X86ISD::XOR; break;
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case ISD::AND: Opcode = X86ISD::AND; break;
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}
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NumOperands = 2;
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break;
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case X86ISD::ADD:
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case X86ISD::SUB:
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case X86ISD::INC:
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case X86ISD::DEC:
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case X86ISD::OR:
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case X86ISD::XOR:
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case X86ISD::AND:
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return SDValue(Op.getNode(), 1);
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default:
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default_case:
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break;
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}
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// Otherwise just emit a CMP with 0, which is the TEST pattern.
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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DAG.getConstant(0, Op.getValueType()));
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if (Opcode == 0)
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// Emit a CMP with 0, which is the TEST pattern.
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return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
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DAG.getConstant(0, Op.getValueType()));
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SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0; i != NumOperands; ++i)
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Ops.push_back(Op.getOperand(i));
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SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
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DAG.ReplaceAllUsesWith(Op, New);
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return SDValue(New.getNode(), 1);
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}
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/// Emit nodes that will be selected as "cmp Op0,Op1", or something
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