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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207503 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2014-04-29 07:57:24 +00:00
parent 47f50878a9
commit c279ae979e
39 changed files with 312 additions and 301 deletions
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6
lib/Target/R600/AMDGPUAsmPrinter.h
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@@ -47,14 +47,14 @@ private:
public: public:
explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer); explicit AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer);
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "AMDGPU Assembly Printer"; return "AMDGPU Assembly Printer";
} }
/// Implemented in AMDGPUMCInstLower.cpp /// Implemented in AMDGPUMCInstLower.cpp
virtual void EmitInstruction(const MachineInstr *MI); void EmitInstruction(const MachineInstr *MI) override;
protected: protected:
bool DisasmEnabled; bool DisasmEnabled;

4
lib/Target/R600/AMDGPUConvertToISA.cpp
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@@ -31,9 +31,9 @@ public:
AMDGPUConvertToISAPass(TargetMachine &tm) : AMDGPUConvertToISAPass(TargetMachine &tm) :
MachineFunctionPass(ID), TM(tm) { } MachineFunctionPass(ID), TM(tm) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {return "AMDGPU Convert to ISA";} const char *getPassName() const override {return "AMDGPU Convert to ISA";}
}; };

13
lib/Target/R600/AMDGPUFrameLowering.h
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@@ -33,12 +33,13 @@ public:
/// \returns The number of 32-bit sub-registers that are used when storing /// \returns The number of 32-bit sub-registers that are used when storing
/// values to the stack. /// values to the stack.
virtual unsigned getStackWidth(const MachineFunction &MF) const; virtual unsigned getStackWidth(const MachineFunction &MF) const final;
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const; int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
virtual const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) const; const SpillSlot *
virtual void emitPrologue(MachineFunction &MF) const; getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitPrologue(MachineFunction &MF) const override;
virtual bool hasFP(const MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
bool hasFP(const MachineFunction &MF) const override;
}; };
} // namespace llvm } // namespace llvm
#endif // AMDILFRAME_LOWERING_H #endif // AMDILFRAME_LOWERING_H

6
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
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@@ -37,9 +37,9 @@ public:
AMDGPUDAGToDAGISel(TargetMachine &TM); AMDGPUDAGToDAGISel(TargetMachine &TM);
virtual ~AMDGPUDAGToDAGISel(); virtual ~AMDGPUDAGToDAGISel();
SDNode *Select(SDNode *N); SDNode *Select(SDNode *N) override;
virtual const char *getPassName() const; const char *getPassName() const override;
virtual void PostprocessISelDAG(); void PostprocessISelDAG() override;
private: private:
bool isInlineImmediate(SDNode *N) const; bool isInlineImmediate(SDNode *N) const;

65
lib/Target/R600/AMDGPUISelLowering.h
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@@ -80,61 +80,62 @@ protected:
public: public:
AMDGPUTargetLowering(TargetMachine &TM); AMDGPUTargetLowering(TargetMachine &TM);
virtual bool isFAbsFree(EVT VT) const override; bool isFAbsFree(EVT VT) const override;
virtual bool isFNegFree(EVT VT) const override; bool isFNegFree(EVT VT) const override;
virtual bool isTruncateFree(EVT Src, EVT Dest) const override; bool isTruncateFree(EVT Src, EVT Dest) const override;
virtual bool isTruncateFree(Type *Src, Type *Dest) const override; bool isTruncateFree(Type *Src, Type *Dest) const override;
virtual bool isZExtFree(Type *Src, Type *Dest) const override; bool isZExtFree(Type *Src, Type *Dest) const override;
virtual bool isZExtFree(EVT Src, EVT Dest) const override; bool isZExtFree(EVT Src, EVT Dest) const override;
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
virtual MVT getVectorIdxTy() const override; MVT getVectorIdxTy() const override;
virtual bool isLoadBitCastBeneficial(EVT, EVT) const override; bool isLoadBitCastBeneficial(EVT, EVT) const override;
virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<SDValue> &OutVals,
SDLoc DL, SelectionDAG &DAG) const; SDLoc DL, SelectionDAG &DAG) const override;
virtual SDValue LowerCall(CallLoweringInfo &CLI, SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual void ReplaceNodeResults(SDNode * N, void ReplaceNodeResults(SDNode * N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
virtual const char* getTargetNodeName(unsigned Opcode) const; const char* getTargetNodeName(unsigned Opcode) const override;
virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const { virtual SDNode *PostISelFolding(MachineSDNode *N,
SelectionDAG &DAG) const {
return N; return N;
} }
/// \brief Determine which of the bits specified in \p Mask are known to be /// \brief Determine which of the bits specified in \p Mask are known to be
/// either zero or one and return them in the \p KnownZero and \p KnownOne /// either zero or one and return them in the \p KnownZero and \p KnownOne
/// bitsets. /// bitsets.
virtual void computeMaskedBitsForTargetNode(const SDValue Op, void computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
unsigned Depth = 0) const override; unsigned Depth = 0) const override;
// Functions defined in AMDILISelLowering.cpp // Functions defined in AMDILISelLowering.cpp
public: public:
virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I, unsigned Intrinsic) const; const CallInst &I, unsigned Intrinsic) const override;
/// We want to mark f32/f64 floating point values as legal. /// We want to mark f32/f64 floating point values as legal.
bool isFPImmLegal(const APFloat &Imm, EVT VT) const; bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
/// We don't want to shrink f64/f32 constants. /// We don't want to shrink f64/f32 constants.
bool ShouldShrinkFPConstant(EVT VT) const; bool ShouldShrinkFPConstant(EVT VT) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
private: private:
void InitAMDILLowering(); void InitAMDILLowering();

72
lib/Target/R600/AMDGPUInstrInfo.h
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@@ -52,14 +52,15 @@ public:
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
unsigned &DstReg, unsigned &SubIdx) const; unsigned &DstReg, unsigned &SubIdx) const override;
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
bool hasLoadFromStackSlot(const MachineInstr *MI, bool hasLoadFromStackSlot(const MachineInstr *MI,
const MachineMemOperand *&MMO, const MachineMemOperand *&MMO,
int &FrameIndex) const; int &FrameIndex) const override;
unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const;
@@ -70,7 +71,7 @@ public:
MachineInstr * MachineInstr *
convertToThreeAddress(MachineFunction::iterator &MFI, convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI, MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const; LiveVariables *LV) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, virtual void copyPhysReg(MachineBasicBlock &MBB,
@@ -78,61 +79,62 @@ public:
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const = 0; bool KillSrc) const = 0;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
protected: protected:
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops, const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const; int FrameIndex) const override;
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops, const SmallVectorImpl<unsigned> &Ops,
MachineInstr *LoadMI) const; MachineInstr *LoadMI) const override;
/// \returns the smallest register index that will be accessed by an indirect /// \returns the smallest register index that will be accessed by an indirect
/// read or write or -1 if indirect addressing is not used by this program. /// read or write or -1 if indirect addressing is not used by this program.
virtual int getIndirectIndexBegin(const MachineFunction &MF) const; virtual int getIndirectIndexBegin(const MachineFunction &MF) const final;
/// \returns the largest register index that will be accessed by an indirect /// \returns the largest register index that will be accessed by an indirect
/// read or write or -1 if indirect addressing is not used by this program. /// read or write or -1 if indirect addressing is not used by this program.
virtual int getIndirectIndexEnd(const MachineFunction &MF) const; virtual int getIndirectIndexEnd(const MachineFunction &MF) const final;
public: public:
bool canFoldMemoryOperand(const MachineInstr *MI, bool canFoldMemoryOperand(const MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops) const; const SmallVectorImpl<unsigned> &Ops) const override;
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
unsigned Reg, bool UnfoldLoad, bool UnfoldStore, unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
SmallVectorImpl<MachineInstr *> &NewMIs) const; SmallVectorImpl<MachineInstr *> &NewMIs) const override;
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
SmallVectorImpl<SDNode *> &NewNodes) const; SmallVectorImpl<SDNode *> &NewNodes) const override;
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
bool UnfoldLoad, bool UnfoldStore, bool UnfoldLoad, bool UnfoldStore,
unsigned *LoadRegIndex = nullptr) const; unsigned *LoadRegIndex = nullptr) const override;
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2, int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const; unsigned NumLoads) const override;
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
void insertNoop(MachineBasicBlock &MBB, void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const; MachineBasicBlock::iterator MI) const override;
bool isPredicated(const MachineInstr *MI) const; bool isPredicated(const MachineInstr *MI) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const; const SmallVectorImpl<MachineOperand> &Pred2) const override;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const; std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr *MI) const; bool isPredicable(MachineInstr *MI) const override;
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
// Helper functions that check the opcode for status information // Helper functions that check the opcode for status information
bool isLoadInst(llvm::MachineInstr *MI) const; bool isLoadInst(llvm::MachineInstr *MI) const;
@@ -187,7 +189,7 @@ public:
/// \brief Convert the AMDIL MachineInstr to a supported ISA /// \brief Convert the AMDIL MachineInstr to a supported ISA
/// MachineInstr /// MachineInstr
virtual void convertToISA(MachineInstr & MI, MachineFunction &MF, virtual void convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const; DebugLoc DL) const final;
/// \brief Build a MOV instruction. /// \brief Build a MOV instruction.
virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB, virtual MachineInstr *buildMovInstr(MachineBasicBlock *MBB,

8
lib/Target/R600/AMDGPURegisterInfo.h
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@@ -34,7 +34,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
AMDGPURegisterInfo(TargetMachine &tm); AMDGPURegisterInfo(TargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const { BitVector getReservedRegs(const MachineFunction &MF) const override {
assert(!"Unimplemented"); return BitVector(); assert(!"Unimplemented"); return BitVector();
} }
@@ -58,11 +58,11 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
unsigned getSubRegFromChannel(unsigned Channel) const; unsigned getSubRegFromChannel(unsigned Channel) const;
const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const; const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum, unsigned FIOperandNum,
RegScavenger *RS) const; RegScavenger *RS) const override;
unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getFrameRegister(const MachineFunction &MF) const override;
unsigned getIndirectSubReg(unsigned IndirectIndex) const; unsigned getIndirectSubReg(unsigned IndirectIndex) const;

6
lib/Target/R600/AMDGPUSubtarget.h
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@@ -60,7 +60,7 @@ public:
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS); virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS) final;
bool is64bit() const; bool is64bit() const;
bool hasVertexCache() const; bool hasVertexCache() const;
@@ -92,14 +92,14 @@ public:
unsigned getStackEntrySize() const; unsigned getStackEntrySize() const;
bool hasCFAluBug() const; bool hasCFAluBug() const;
virtual bool enableMachineScheduler() const { bool enableMachineScheduler() const override {
return getGeneration() <= NORTHERN_ISLANDS; return getGeneration() <= NORTHERN_ISLANDS;
} }
// Helper functions to simplify if statements // Helper functions to simplify if statements
bool isTargetELF() const; bool isTargetELF() const;
std::string getDeviceName() const; std::string getDeviceName() const;
virtual size_t getDefaultSize(uint32_t dim) const; virtual size_t getDefaultSize(uint32_t dim) const final;
bool dumpCode() const { return DumpCode; } bool dumpCode() const { return DumpCode; }
bool r600ALUEncoding() const { return R600ALUInst; } bool r600ALUEncoding() const { return R600ALUInst; }

16
lib/Target/R600/AMDGPUTargetMachine.cpp
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@@ -103,20 +103,20 @@ public:
return getTM<AMDGPUTargetMachine>(); return getTM<AMDGPUTargetMachine>();
} }
virtual ScheduleDAGInstrs * ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const { createMachineScheduler(MachineSchedContext *C) const override {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
return createR600MachineScheduler(C); return createR600MachineScheduler(C);
return nullptr; return nullptr;
} }
virtual bool addPreISel(); bool addPreISel() override;
virtual bool addInstSelector(); bool addInstSelector() override;
virtual bool addPreRegAlloc(); bool addPreRegAlloc() override;
virtual bool addPostRegAlloc(); bool addPostRegAlloc() override;
virtual bool addPreSched2(); bool addPreSched2() override;
virtual bool addPreEmitPass(); bool addPreEmitPass() override;
}; };
} // End of anonymous namespace } // End of anonymous namespace

22
lib/Target/R600/AMDGPUTargetMachine.h
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@@ -39,30 +39,32 @@ public:
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine(); ~AMDGPUTargetMachine();
virtual const AMDGPUFrameLowering *getFrameLowering() const { const AMDGPUFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
return &IntrinsicInfo; return &IntrinsicInfo;
} }
virtual const AMDGPUInstrInfo *getInstrInfo() const { const AMDGPUInstrInfo *getInstrInfo() const override {
return InstrInfo.get(); return InstrInfo.get();
} }
virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } const AMDGPUSubtarget *getSubtargetImpl() const override {
virtual const AMDGPURegisterInfo *getRegisterInfo() const { return &Subtarget;
}
const AMDGPURegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo(); return &InstrInfo->getRegisterInfo();
} }
virtual AMDGPUTargetLowering *getTargetLowering() const { AMDGPUTargetLowering *getTargetLowering() const override {
return TLInfo.get(); return TLInfo.get();
} }
virtual const InstrItineraryData *getInstrItineraryData() const { const InstrItineraryData *getInstrItineraryData() const override {
return InstrItins; return InstrItins;
} }
virtual const DataLayout *getDataLayout() const { return &Layout; } const DataLayout *getDataLayout() const override { return &Layout; }
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// \brief Register R600 analysis passes with a pass manager. /// \brief Register R600 analysis passes with a pass manager.
virtual void addAnalysisPasses(PassManagerBase &PM); void addAnalysisPasses(PassManagerBase &PM) override;
}; };
} // End namespace llvm } // End namespace llvm

11
lib/Target/R600/AMDGPUTargetTransformInfo.cpp
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@@ -56,9 +56,9 @@ public:
initializeAMDGPUTTIPass(*PassRegistry::getPassRegistry()); initializeAMDGPUTTIPass(*PassRegistry::getPassRegistry());
} }
virtual void initializePass() override { pushTTIStack(this); } void initializePass() override { pushTTIStack(this); }
virtual void getAnalysisUsage(AnalysisUsage &AU) const override { void getAnalysisUsage(AnalysisUsage &AU) const override {
TargetTransformInfo::getAnalysisUsage(AU); TargetTransformInfo::getAnalysisUsage(AU);
} }
@@ -66,15 +66,16 @@ public:
static char ID; static char ID;
/// Provide necessary pointer adjustments for the two base classes. /// Provide necessary pointer adjustments for the two base classes.
virtual void *getAdjustedAnalysisPointer(const void *ID) override { void *getAdjustedAnalysisPointer(const void *ID) override {
if (ID == &TargetTransformInfo::ID) if (ID == &TargetTransformInfo::ID)
return (TargetTransformInfo *)this; return (TargetTransformInfo *)this;
return this; return this;
} }
virtual bool hasBranchDivergence() const override; bool hasBranchDivergence() const override;
virtual void getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const; void getUnrollingPreferences(Loop *L,
UnrollingPreferences &UP) const override;
/// @} /// @}
}; };

6
lib/Target/R600/AMDILCFGStructurizer.cpp
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@@ -139,11 +139,11 @@ public:
initializeAMDGPUCFGStructurizerPass(*PassRegistry::getPassRegistry()); initializeAMDGPUCFGStructurizerPass(*PassRegistry::getPassRegistry());
} }
const char *getPassName() const { const char *getPassName() const override {
return "AMDGPU Control Flow Graph structurizer Pass"; return "AMDGPU Control Flow Graph structurizer Pass";
} }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addPreserved<MachineFunctionAnalysis>(); AU.addPreserved<MachineFunctionAnalysis>();
AU.addRequired<MachineFunctionAnalysis>(); AU.addRequired<MachineFunctionAnalysis>();
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
@@ -159,7 +159,7 @@ public:
/// sure all loops have an exit block /// sure all loops have an exit block
bool prepare(); bool prepare();
bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
TRI = &TII->getRegisterInfo(); TRI = &TII->getRegisterInfo();
DEBUG(MF.dump();); DEBUG(MF.dump(););

8
lib/Target/R600/AMDILIntrinsicInfo.h
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@@ -35,12 +35,12 @@ class AMDGPUIntrinsicInfo : public TargetIntrinsicInfo {
public: public:
AMDGPUIntrinsicInfo(TargetMachine *tm); AMDGPUIntrinsicInfo(TargetMachine *tm);
std::string getName(unsigned int IntrId, Type **Tys = nullptr, std::string getName(unsigned int IntrId, Type **Tys = nullptr,
unsigned int numTys = 0) const; unsigned int numTys = 0) const override;
unsigned int lookupName(const char *Name, unsigned int Len) const; unsigned int lookupName(const char *Name, unsigned int Len) const override;
bool isOverloaded(unsigned int IID) const; bool isOverloaded(unsigned int IID) const override;
Function *getDeclaration(Module *M, unsigned int ID, Function *getDeclaration(Module *M, unsigned int ID,
Type **Tys = nullptr, Type **Tys = nullptr,
unsigned int numTys = 0) const; unsigned int numTys = 0) const override;
}; };
} // end namespace llvm } // end namespace llvm

2
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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@@ -29,7 +29,7 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo);
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
private: private:
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

26
lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
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@@ -23,8 +23,8 @@ namespace {
class AMDGPUMCObjectWriter : public MCObjectWriter { class AMDGPUMCObjectWriter : public MCObjectWriter {
public: public:
AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { } AMDGPUMCObjectWriter(raw_ostream &OS) : MCObjectWriter(OS, true) { }
virtual void ExecutePostLayoutBinding(MCAssembler &Asm, void ExecutePostLayoutBinding(MCAssembler &Asm,
const MCAsmLayout &Layout) { const MCAsmLayout &Layout) override {
//XXX: Implement if necessary. //XXX: Implement if necessary.
} }
void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
@@ -34,7 +34,7 @@ public:
assert(!"Not implemented"); assert(!"Not implemented");
} }
virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout); void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) override;
}; };
@@ -43,19 +43,19 @@ public:
AMDGPUAsmBackend(const Target &T) AMDGPUAsmBackend(const Target &T)
: MCAsmBackend() {} : MCAsmBackend() {}
virtual unsigned getNumFixupKinds() const { return 0; }; unsigned getNumFixupKinds() const override { return 0; };
virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const; uint64_t Value, bool IsPCRel) const override;
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF, const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const { const MCAsmLayout &Layout) const override {
return false; return false;
} }
virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const { void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
assert(!"Not implemented"); assert(!"Not implemented");
} }
virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; } bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
return true; return true;
} }
}; };
@@ -88,7 +88,7 @@ class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
public: public:
ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { } ELFAMDGPUAsmBackend(const Target &T) : AMDGPUAsmBackend(T) { }
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
return createAMDGPUELFObjectWriter(OS); return createAMDGPUELFObjectWriter(OS);
} }
}; };

2
lib/Target/R600/MCTargetDesc/AMDGPUMCAsmInfo.h
View File

@@ -22,7 +22,7 @@ class StringRef;
class AMDGPUMCAsmInfo : public MCAsmInfo { class AMDGPUMCAsmInfo : public MCAsmInfo {
public: public:
explicit AMDGPUMCAsmInfo(StringRef &TT); explicit AMDGPUMCAsmInfo(StringRef &TT);
const MCSection* getNonexecutableStackSection(MCContext &CTX) const; const MCSection* getNonexecutableStackSection(MCContext &CTX) const override;
}; };
} // namespace llvm } // namespace llvm
#endif // AMDGPUMCASMINFO_H #endif // AMDGPUMCASMINFO_H

10
lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
View File

@@ -41,14 +41,14 @@ public:
: MCII(mcii), MRI(mri) { } : MCII(mcii), MRI(mri) { }
/// \brief Encode the instruction and write it to the OS. /// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
/// \returns the encoding for an MCOperand. /// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
private: private:
void EmitByte(unsigned int byte, raw_ostream &OS) const; void EmitByte(unsigned int byte, raw_ostream &OS) const;

10
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@@ -54,14 +54,14 @@ public:
~SIMCCodeEmitter() { } ~SIMCCodeEmitter() { }
/// \brief Encode the instruction and write it to the OS. /// \brief Encode the instruction and write it to the OS.
virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
/// \returns the encoding for an MCOperand. /// \returns the encoding for an MCOperand.
virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
}; };
} // End anonymous namespace } // End anonymous namespace

4
lib/Target/R600/R600ClauseMergePass.cpp
View File

@@ -63,9 +63,9 @@ private:
public: public:
R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { } R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const; const char *getPassName() const override;
}; };
char R600ClauseMergePass::ID = 0; char R600ClauseMergePass::ID = 0;

4
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@@ -475,7 +475,7 @@ public:
MaxFetchInst = ST.getTexVTXClauseSize(); MaxFetchInst = ST.getTexVTXClauseSize();
} }
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo()); TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>(); R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
@@ -666,7 +666,7 @@ public:
return false; return false;
} }
const char *getPassName() const { const char *getPassName() const override {
return "R600 Control Flow Finalizer Pass"; return "R600 Control Flow Finalizer Pass";
} }
}; };

4
lib/Target/R600/R600EmitClauseMarkers.cpp
View File

@@ -296,7 +296,7 @@ public:
initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry()); initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnMachineFunction(MachineFunction &MF) { bool runOnMachineFunction(MachineFunction &MF) override {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo()); TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
@@ -315,7 +315,7 @@ public:
return false; return false;
} }
const char *getPassName() const { const char *getPassName() const override {
return "R600 Emit Clause Markers Pass"; return "R600 Emit Clause Markers Pass";
} }
}; };

4
lib/Target/R600/R600ExpandSpecialInstrs.cpp
View File

@@ -40,9 +40,9 @@ public:
R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID), R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
TII(nullptr) { } TII(nullptr) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { const char *getPassName() const override {
return "R600 Expand special instructions pass"; return "R600 Expand special instructions pass";
} }
}; };

32
lib/Target/R600/R600ISelLowering.h
View File

@@ -24,21 +24,21 @@ class R600InstrInfo;
class R600TargetLowering : public AMDGPUTargetLowering { class R600TargetLowering : public AMDGPUTargetLowering {
public: public:
R600TargetLowering(TargetMachine &TM); R600TargetLowering(TargetMachine &TM);
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock * BB) const; MachineBasicBlock * BB) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual void ReplaceNodeResults(SDNode * N, void ReplaceNodeResults(SDNode * N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
virtual SDValue LowerFormalArguments( SDValue LowerFormalArguments(
SDValue Chain, SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc DL, SelectionDAG &DAG, SDLoc DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const; EVT getSetCCResultType(LLVMContext &, EVT VT) const override;
private: private:
unsigned Gen; unsigned Gen;
/// Each OpenCL kernel has nine implicit parameters that are stored in the /// Each OpenCL kernel has nine implicit parameters that are stored in the
@@ -66,7 +66,7 @@ private:
void getStackAddress(unsigned StackWidth, unsigned ElemIdx, void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
unsigned &Channel, unsigned &PtrIncr) const; unsigned &Channel, unsigned &PtrIncr) const;
bool isZero(SDValue Op) const; bool isZero(SDValue Op) const;
virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const; SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
}; };
} // End namespace llvm; } // End namespace llvm;

76
lib/Target/R600/R600InstrInfo.h
View File

@@ -50,13 +50,13 @@ namespace llvm {
explicit R600InstrInfo(AMDGPUTargetMachine &tm); explicit R600InstrInfo(AMDGPUTargetMachine &tm);
const R600RegisterInfo &getRegisterInfo() const; const R600RegisterInfo &getRegisterInfo() const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const; MachineBasicBlock::iterator MBBI) const override;
bool isTrig(const MachineInstr &MI) const; bool isTrig(const MachineInstr &MI) const;
bool isPlaceHolderOpcode(unsigned opcode) const; bool isPlaceHolderOpcode(unsigned opcode) const;
@@ -142,79 +142,79 @@ namespace llvm {
/// instruction slots within an instruction group. /// instruction slots within an instruction group.
bool isVector(const MachineInstr &MI) const; bool isVector(const MachineInstr &MI) const;
virtual unsigned getIEQOpcode() const; unsigned getIEQOpcode() const override;
virtual bool isMov(unsigned Opcode) const; bool isMov(unsigned Opcode) const override;
DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const; const ScheduleDAG *DAG) const override;
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
bool isPredicated(const MachineInstr *MI) const; bool isPredicated(const MachineInstr *MI) const override;
bool isPredicable(MachineInstr *MI) const; bool isPredicable(MachineInstr *MI) const override;
bool bool
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
const BranchProbability &Probability) const; const BranchProbability &Probability) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const ; const BranchProbability &Probability) const override ;
bool bool
isProfitableToIfCvt(MachineBasicBlock &TMBB, isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumTCycles, unsigned ExtraTCycles, unsigned NumTCycles, unsigned ExtraTCycles,
MachineBasicBlock &FMBB, MachineBasicBlock &FMBB,
unsigned NumFCycles, unsigned ExtraFCycles, unsigned NumFCycles, unsigned ExtraFCycles,
const BranchProbability &Probability) const; const BranchProbability &Probability) const override;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const; std::vector<MachineOperand> &Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const; const SmallVectorImpl<MachineOperand> &Pred2) const override;
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const; MachineBasicBlock &FMBB) const override;
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const; const SmallVectorImpl<MachineOperand> &Pred) const override;
unsigned int getPredicationCost(const MachineInstr *) const; unsigned int getPredicationCost(const MachineInstr *) const override;
unsigned int getInstrLatency(const InstrItineraryData *ItinData, unsigned int getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI, const MachineInstr *MI,
unsigned *PredCost = nullptr) const; unsigned *PredCost = nullptr) const override;
virtual int getInstrLatency(const InstrItineraryData *ItinData, int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const { return 1;} SDNode *Node) const override { return 1;}
/// \brief Reserve the registers that may be accesed using indirect addressing. /// \brief Reserve the registers that may be accesed using indirect addressing.
void reserveIndirectRegisters(BitVector &Reserved, void reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const; const MachineFunction &MF) const;
virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const; unsigned Channel) const override;
virtual const TargetRegisterClass *getIndirectAddrRegClass() const; const TargetRegisterClass *getIndirectAddrRegClass() const override;
virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address, unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const; unsigned OffsetReg) const override;
virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned Address, unsigned ValueReg, unsigned Address,
unsigned OffsetReg) const; unsigned OffsetReg) const override;
unsigned getMaxAlusPerClause() const; unsigned getMaxAlusPerClause() const;
@@ -244,7 +244,7 @@ namespace llvm {
MachineInstr *buildMovInstr(MachineBasicBlock *MBB, MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DstReg, unsigned SrcReg) const; unsigned DstReg, unsigned SrcReg) const override;
/// \brief Get the index of Op in the MachineInstr. /// \brief Get the index of Op in the MachineInstr.
/// ///

2
lib/Target/R600/R600MachineFunctionInfo.h
View File

@@ -21,7 +21,7 @@
namespace llvm { namespace llvm {
class R600MachineFunctionInfo : public AMDGPUMachineFunction { class R600MachineFunctionInfo : public AMDGPUMachineFunction {
virtual void anchor(); void anchor() override;
public: public:
R600MachineFunctionInfo(const MachineFunction &MF); R600MachineFunctionInfo(const MachineFunction &MF);
SmallVector<unsigned, 4> LiveOuts; SmallVector<unsigned, 4> LiveOuts;

13
lib/Target/R600/R600MachineScheduler.h
View File

@@ -71,14 +71,13 @@ public:
DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) { DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
} }
virtual ~R600SchedStrategy() { virtual ~R600SchedStrategy() {}
}
virtual void initialize(ScheduleDAGMI *dag); void initialize(ScheduleDAGMI *dag) override;
virtual SUnit *pickNode(bool &IsTopNode); SUnit *pickNode(bool &IsTopNode) override;
virtual void schedNode(SUnit *SU, bool IsTopNode); void schedNode(SUnit *SU, bool IsTopNode) override;
virtual void releaseTopNode(SUnit *SU); void releaseTopNode(SUnit *SU) override;
virtual void releaseBottomNode(SUnit *SU); void releaseBottomNode(SUnit *SU) override;
private: private:
std::vector<MachineInstr *> InstructionsGroupCandidate; std::vector<MachineInstr *> InstructionsGroupCandidate;

6
lib/Target/R600/R600OptimizeVectorRegisters.cpp
View File

@@ -110,7 +110,7 @@ public:
R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID), R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
TII(nullptr) { } TII(nullptr) { }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>(); AU.addPreserved<MachineDominatorTree>();
@@ -119,11 +119,11 @@ public:
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const { const char *getPassName() const override {
return "R600 Vector Registers Merge Pass"; return "R600 Vector Registers Merge Pass";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };
char R600VectorRegMerger::ID = 0; char R600VectorRegMerger::ID = 0;

21
lib/Target/R600/R600Packetizer.cpp
View File

@@ -37,7 +37,7 @@ public:
static char ID; static char ID;
R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {} R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>(); AU.addPreserved<MachineDominatorTree>();
@@ -46,11 +46,11 @@ public:
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const { const char *getPassName() const override {
return "R600 Packetizer"; return "R600 Packetizer";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };
char R600Packetizer::ID = 0; char R600Packetizer::ID = 0;
@@ -156,18 +156,19 @@ public:
} }
// initPacketizerState - initialize some internal flags. // initPacketizerState - initialize some internal flags.
void initPacketizerState() { void initPacketizerState() override {
ConsideredInstUsesAlreadyWrittenVectorElement = false; ConsideredInstUsesAlreadyWrittenVectorElement = false;
} }
// ignorePseudoInstruction - Ignore bundling of pseudo instructions. // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) { bool ignorePseudoInstruction(MachineInstr *MI,
MachineBasicBlock *MBB) override {
return false; return false;
} }
// isSoloInstruction - return true if instruction MI can not be packetized // isSoloInstruction - return true if instruction MI can not be packetized
// with any other instruction, which means that MI itself is a packet. // with any other instruction, which means that MI itself is a packet.
bool isSoloInstruction(MachineInstr *MI) { bool isSoloInstruction(MachineInstr *MI) override {
if (TII->isVector(*MI)) if (TII->isVector(*MI))
return true; return true;
if (!TII->isALUInstr(MI->getOpcode())) if (!TII->isALUInstr(MI->getOpcode()))
@@ -183,7 +184,7 @@ public:
// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
// together. // together.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr(); MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
if (getSlot(MII) == getSlot(MIJ)) if (getSlot(MII) == getSlot(MIJ))
ConsideredInstUsesAlreadyWrittenVectorElement = true; ConsideredInstUsesAlreadyWrittenVectorElement = true;
@@ -220,7 +221,9 @@ public:
// isLegalToPruneDependencies - Is it legal to prune dependece between SUI // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
// and SUJ. // and SUJ.
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;} bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
return false;
}
void setIsLastBit(MachineInstr *MI, unsigned Bit) const { void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last); unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
@@ -289,7 +292,7 @@ public:
return true; return true;
} }
MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override {
MachineBasicBlock::iterator FirstInBundle = MachineBasicBlock::iterator FirstInBundle =
CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front(); CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
const DenseMap<unsigned, unsigned> &PV = const DenseMap<unsigned, unsigned> &PV =

15
lib/Target/R600/R600RegisterInfo.h
View File

@@ -28,27 +28,28 @@ struct R600RegisterInfo : public AMDGPURegisterInfo {
R600RegisterInfo(AMDGPUTargetMachine &tm); R600RegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
/// \param RC is an AMDIL reg class. /// \param RC is an AMDIL reg class.
/// ///
/// \returns the R600 reg class that is equivalent to \p RC. /// \returns the R600 reg class that is equivalent to \p RC.
virtual const TargetRegisterClass *getISARegClass( const TargetRegisterClass *getISARegClass(
const TargetRegisterClass *RC) const; const TargetRegisterClass *RC) const override;
/// \brief get the HW encoding for a register's channel. /// \brief get the HW encoding for a register's channel.
unsigned getHWRegChan(unsigned reg) const; unsigned getHWRegChan(unsigned reg) const;
virtual unsigned getHWRegIndex(unsigned Reg) const; unsigned getHWRegIndex(unsigned Reg) const override;
/// \brief get the register class of the specified type to use in the /// \brief get the register class of the specified type to use in the
/// CFGStructurizer /// CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const; const RegClassWeight &
getRegClassWeight(const TargetRegisterClass *RC) const override;
// \returns true if \p Reg can be defined in one ALU caluse and used in another. // \returns true if \p Reg can be defined in one ALU caluse and used in another.
virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const; virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const final;
}; };
} // End namespace llvm } // End namespace llvm

8
lib/Target/R600/R600TextureIntrinsicsReplacer.cpp
View File

@@ -209,7 +209,7 @@ public:
FunctionPass(ID) { FunctionPass(ID) {
} }
virtual bool doInitialization(Module &M) { bool doInitialization(Module &M) override {
LLVMContext &Ctx = M.getContext(); LLVMContext &Ctx = M.getContext();
Mod = &M; Mod = &M;
FloatType = Type::getFloatTy(Ctx); FloatType = Type::getFloatTy(Ctx);
@@ -245,16 +245,16 @@ public:
return false; return false;
} }
virtual bool runOnFunction(Function &F) { bool runOnFunction(Function &F) override {
visit(F); visit(F);
return false; return false;
} }
virtual const char *getPassName() const { const char *getPassName() const override {
return "R600 Texture Intrinsics Replacer"; return "R600 Texture Intrinsics Replacer";
} }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
} }
void visitCallInst(CallInst &I) { void visitCallInst(CallInst &I) {

8
lib/Target/R600/SIAnnotateControlFlow.cpp
View File

@@ -91,15 +91,15 @@ public:
SIAnnotateControlFlow(): SIAnnotateControlFlow():
FunctionPass(ID) { } FunctionPass(ID) { }
virtual bool doInitialization(Module &M); bool doInitialization(Module &M) override;
virtual bool runOnFunction(Function &F); bool runOnFunction(Function &F) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "SI annotate control flow"; return "SI annotate control flow";
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<DominatorTreeWrapperPass>(); AU.addRequired<DominatorTreeWrapperPass>();
AU.addPreserved<DominatorTreeWrapperPass>(); AU.addPreserved<DominatorTreeWrapperPass>();
FunctionPass::getAnalysisUsage(AU); FunctionPass::getAnalysisUsage(AU);

4
lib/Target/R600/SIFixSGPRCopies.cpp
View File

@@ -98,9 +98,9 @@ private:
public: public:
SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { } SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { const char *getPassName() const override {
return "SI Fix SGPR copies"; return "SI Fix SGPR copies";
} }

33
lib/Target/R600/SIISelLowering.h
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@@ -48,32 +48,33 @@ class SITargetLowering : public AMDGPUTargetLowering {
public: public:
SITargetLowering(TargetMachine &tm); SITargetLowering(TargetMachine &tm);
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const; bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
virtual bool shouldSplitVectorType(EVT VT) const override; bool *IsFast) const override;
bool shouldSplitVectorType(EVT VT) const override;
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override; Type *Ty) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc DL, SelectionDAG &DAG, SDLoc DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
MachineBasicBlock * BB) const; MachineBasicBlock * BB) const override;
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
virtual MVT getScalarShiftAmountTy(EVT VT) const; MVT getScalarShiftAmountTy(EVT VT) const override;
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const; SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
virtual void AdjustInstrPostInstrSelection(MachineInstr *MI, void AdjustInstrPostInstrSelection(MachineInstr *MI,
SDNode *Node) const; SDNode *Node) const override;
int32_t analyzeImmediate(const SDNode *N) const; int32_t analyzeImmediate(const SDNode *N) const;
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
unsigned Reg, EVT VT) const; unsigned Reg, EVT VT) const override;
}; };
} // End namespace llvm } // End namespace llvm

4
lib/Target/R600/SIInsertWaits.cpp
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@@ -101,9 +101,9 @@ public:
TRI(nullptr), TRI(nullptr),
ExpInstrTypesSeen(0) { } ExpInstrTypesSeen(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { const char *getPassName() const override {
return "SI insert wait instructions"; return "SI insert wait instructions";
} }

56
lib/Target/R600/SIInstrInfo.h
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@@ -52,45 +52,45 @@ private:
public: public:
explicit SIInstrInfo(AMDGPUTargetMachine &tm); explicit SIInstrInfo(AMDGPUTargetMachine &tm);
const SIRegisterInfo &getRegisterInfo() const { const SIRegisterInfo &getRegisterInfo() const override {
return RI; return RI;
} }
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
unsigned commuteOpcode(unsigned Opcode) const; unsigned commuteOpcode(unsigned Opcode) const;
virtual MachineInstr *commuteInstruction(MachineInstr *MI, MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI=false) const; bool NewMI=false) const override;
bool isTriviallyReMaterializable(const MachineInstr *MI, bool isTriviallyReMaterializable(const MachineInstr *MI,
AliasAnalysis *AA = nullptr) const; AliasAnalysis *AA = nullptr) const;
virtual unsigned getIEQOpcode() const { unsigned getIEQOpcode() const override {
llvm_unreachable("Unimplemented"); llvm_unreachable("Unimplemented");
} }
MachineInstr *buildMovInstr(MachineBasicBlock *MBB, MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DstReg, unsigned SrcReg) const; unsigned DstReg, unsigned SrcReg) const override;
virtual bool isMov(unsigned Opcode) const; bool isMov(unsigned Opcode) const override;
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
bool isDS(uint16_t Opcode) const; bool isDS(uint16_t Opcode) const;
int isMIMG(uint16_t Opcode) const; int isMIMG(uint16_t Opcode) const;
int isSMRD(uint16_t Opcode) const; int isSMRD(uint16_t Opcode) const;
@@ -102,8 +102,8 @@ public:
bool isInlineConstant(const MachineOperand &MO) const; bool isInlineConstant(const MachineOperand &MO) const;
bool isLiteralConstant(const MachineOperand &MO) const; bool isLiteralConstant(const MachineOperand &MO) const;
virtual bool verifyInstruction(const MachineInstr *MI, bool verifyInstruction(const MachineInstr *MI,
StringRef &ErrInfo) const; StringRef &ErrInfo) const override;
bool isSALUInstr(const MachineInstr &MI) const; bool isSALUInstr(const MachineInstr &MI) const;
static unsigned getVALUOp(const MachineInstr &MI); static unsigned getVALUOp(const MachineInstr &MI);
@@ -142,22 +142,22 @@ public:
/// VALU if necessary. /// VALU if necessary.
void moveToVALU(MachineInstr &MI) const; void moveToVALU(MachineInstr &MI) const;
virtual unsigned calculateIndirectAddress(unsigned RegIndex, unsigned calculateIndirectAddress(unsigned RegIndex,
unsigned Channel) const; unsigned Channel) const override;
virtual const TargetRegisterClass *getIndirectAddrRegClass() const; const TargetRegisterClass *getIndirectAddrRegClass() const override;
virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned ValueReg,
unsigned Address, unsigned Address,
unsigned OffsetReg) const; unsigned OffsetReg) const override;
virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned ValueReg, unsigned ValueReg,
unsigned Address, unsigned Address,
unsigned OffsetReg) const; unsigned OffsetReg) const override;
void reserveIndirectRegisters(BitVector &Reserved, void reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const; const MachineFunction &MF) const;

4
lib/Target/R600/SILowerControlFlow.cpp
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@@ -94,9 +94,9 @@ public:
SILowerControlFlowPass(TargetMachine &tm) : SILowerControlFlowPass(TargetMachine &tm) :
MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { const char *getPassName() const override {
return "SI Lower control flow instructions"; return "SI Lower control flow instructions";
} }

2
lib/Target/R600/SIMachineFunctionInfo.h
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@@ -25,7 +25,7 @@ class MachineRegisterInfo;
/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
/// tells the hardware which interpolation parameters to load. /// tells the hardware which interpolation parameters to load.
class SIMachineFunctionInfo : public AMDGPUMachineFunction { class SIMachineFunctionInfo : public AMDGPUMachineFunction {
virtual void anchor(); void anchor() override;
public: public:
struct SpilledReg { struct SpilledReg {

14
lib/Target/R600/SIRegisterInfo.h
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@@ -27,22 +27,22 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
SIRegisterInfo(AMDGPUTargetMachine &tm); SIRegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const; MachineFunction &MF) const override;
/// \param RC is an AMDIL reg class. /// \param RC is an AMDIL reg class.
/// ///
/// \returns the SI register class that is equivalent to \p RC. /// \returns the SI register class that is equivalent to \p RC.
virtual const TargetRegisterClass * const TargetRegisterClass *
getISARegClass(const TargetRegisterClass *RC) const; getISARegClass(const TargetRegisterClass *RC) const override;
/// \brief get the register class of the specified type to use in the /// \brief get the register class of the specified type to use in the
/// CFGStructurizer /// CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
virtual unsigned getHWRegIndex(unsigned Reg) const; unsigned getHWRegIndex(unsigned Reg) const override;
/// \brief Return the 'base' register class for this register. /// \brief Return the 'base' register class for this register.
/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc. /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.

6
lib/Target/R600/SITypeRewriter.cpp
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@@ -39,9 +39,9 @@ class SITypeRewriter : public FunctionPass,
public: public:
SITypeRewriter() : FunctionPass(ID) { } SITypeRewriter() : FunctionPass(ID) { }
virtual bool doInitialization(Module &M); bool doInitialization(Module &M) override;
virtual bool runOnFunction(Function &F); bool runOnFunction(Function &F) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "SI Type Rewriter"; return "SI Type Rewriter";
} }
void visitLoadInst(LoadInst &I); void visitLoadInst(LoadInst &I);