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Fix naming inconsistency.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-01-02 21:33:40 +00:00
parent ad93d7fda5
commit c2b861da18
12 changed files with 57 additions and 57 deletions
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12
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@@ -157,23 +157,23 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
return NULL;
}
const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = {
ARM::R4, ARM::R5, ARM::R6, ARM::R7,
ARM::R8, ARM::R9, ARM::R10, ARM::R11,
ARM::R14, 0
};
return CalleeSaveRegs;
return CalleeSavedRegs;
}
const TargetRegisterClass* const *
ARMRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
ARMRegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
&ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
&ARM::IntRegsRegClass, 0
};
return CalleeSaveRegClasses;
return CalleeSavedRegClasses;
}
void ARMRegisterInfo::

4
lib/Target/ARM/ARMRegisterInfo.h
View File

@@ -47,9 +47,9 @@ struct ARMRegisterInfo : public ARMGenRegisterInfo {
unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,

12
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@@ -151,8 +151,8 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = {
Alpha::R9, Alpha::R10,
Alpha::R11, Alpha::R12,
Alpha::R13, Alpha::R14,
@@ -161,12 +161,12 @@ const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
Alpha::F6, Alpha::F7,
Alpha::F8, Alpha::F9, 0
};
return CalleeSaveRegs;
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
AlphaRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
AlphaRegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
@@ -175,7 +175,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const {
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
};
return CalleeSaveRegClasses;
return CalleeSavedRegClasses;
}
//===----------------------------------------------------------------------===//

4
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@@ -45,9 +45,9 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,

12
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@@ -91,19 +91,19 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
}
const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = {
IA64::r5, 0
};
return CalleeSaveRegs;
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
IA64RegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
IA64RegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
&IA64::GRRegClass, 0
};
return CalleeSaveRegClasses;
return CalleeSavedRegClasses;
}
//===----------------------------------------------------------------------===//

4
lib/Target/IA64/IA64RegisterInfo.h
View File

@@ -44,9 +44,9 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,

20
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@@ -238,9 +238,9 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
// 32-bit Darwin calling convention.
static const unsigned Darwin32_CalleeSaveRegs[] = {
static const unsigned Darwin32_CalleeSavedRegs[] = {
PPC::R13, PPC::R14, PPC::R15,
PPC::R16, PPC::R17, PPC::R18, PPC::R19,
PPC::R20, PPC::R21, PPC::R22, PPC::R23,
@@ -261,7 +261,7 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
PPC::LR, 0
};
// 64-bit Darwin calling convention.
static const unsigned Darwin64_CalleeSaveRegs[] = {
static const unsigned Darwin64_CalleeSavedRegs[] = {
PPC::X14, PPC::X15,
PPC::X16, PPC::X17, PPC::X18, PPC::X19,
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
@@ -282,14 +282,14 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
PPC::LR8, 0
};
return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
Darwin32_CalleeSaveRegs;
return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
Darwin32_CalleeSavedRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSaveRegClasses() const {
PPCRegisterInfo::getCalleeSavedRegClasses() const {
// 32-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = {
static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = {
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
@@ -312,7 +312,7 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const {
};
// 64-bit Darwin calling convention.
static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = {
static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = {
&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
@@ -334,8 +334,8 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const {
&PPC::G8RCRegClass, 0
};
return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
Darwin32_CalleeSaveRegClasses;
return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses :
Darwin32_CalleeSavedRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into

4
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@@ -54,9 +54,9 @@ public:
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,

12
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@@ -111,15 +111,15 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
return NewMI;
}
const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = { 0 };
return CalleeSaveRegs;
const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs[] = { 0 };
return CalleeSavedRegs;
}
const TargetRegisterClass* const*
SparcRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
return CalleeSaveRegClasses;
SparcRegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
return CalleeSavedRegClasses;
}

4
lib/Target/Sparc/SparcRegisterInfo.h
View File

@@ -48,9 +48,9 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,

16
lib/Target/X86/X86RegisterInfo.cpp
View File

@@ -853,30 +853,30 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
}
const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs32Bit[] = {
const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
static const unsigned CalleeSavedRegs32Bit[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
static const unsigned CalleeSaveRegs64Bit[] = {
static const unsigned CalleeSavedRegs64Bit[] = {
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
};
return Is64Bit ? CalleeSaveRegs64Bit : CalleeSaveRegs32Bit;
return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
}
const TargetRegisterClass* const*
X86RegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses32Bit[] = {
X86RegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
&X86::GR32RegClass, &X86::GR32RegClass,
&X86::GR32RegClass, &X86::GR32RegClass, 0
};
static const TargetRegisterClass * const CalleeSaveRegClasses64Bit[] = {
static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
&X86::GR64RegClass, &X86::GR64RegClass,
&X86::GR64RegClass, &X86::GR64RegClass,
&X86::GR64RegClass, &X86::GR64RegClass, 0
};
return Is64Bit ? CalleeSaveRegClasses64Bit : CalleeSaveRegClasses32Bit;
return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
}
//===----------------------------------------------------------------------===//

10
lib/Target/X86/X86RegisterInfo.h
View File

@@ -69,14 +69,14 @@ public:
unsigned OpNum,
int FrameIndex) const;
/// getCalleeSaveRegs - Return a null-terminated list of all of the
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const unsigned *getCalleeSaveRegs() const;
const unsigned *getCalleeSavedRegs() const;
/// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
/// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
/// register classes to spill each callee-saved register with. The order and
/// length of this list match the getCalleeSaveRegs() list.
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
/// length of this list match the getCalleeSavedRegs() list.
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,