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Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lang Hames 2012-02-17 00:27:16 +00:00
parent af8b34dae9
commit c2e08db4e5
2 changed files with 9 additions and 4 deletions
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12
lib/CodeGen/MachineCSE.cpp
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@ -63,6 +63,8 @@ namespace {
virtual void releaseMemory() {
ScopeMap.clear();
Exps.clear();
AllocatableRegs.clear();
ReservedRegs.clear();
}
private:
@ -76,6 +78,8 @@ namespace {
ScopedHTType VNT;
SmallVector<MachineInstr*, 64> Exps;
unsigned CurrVN;
BitVector AllocatableRegs;
BitVector ReservedRegs;
bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
bool isPhysDefTriviallyDead(unsigned Reg,
@ -236,9 +240,9 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
return false;
for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
if (TRI->isInAllocatableClass(PhysDefs[i]))
// Avoid extending live range of physical registers unless
// they are unallocatable.
if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
// Avoid extending live range of physical registers if they are
//allocatable or reserved.
return false;
}
CrossMBB = true;
@ -588,5 +592,7 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
MRI = &MF.getRegInfo();
AA = &getAnalysis<AliasAnalysis>();
DT = &getAnalysis<MachineDominatorTree>();
AllocatableRegs = TRI->getAllocatableSet(MF);
ReservedRegs = TRI->getReservedRegs(MF);
return PerformCSE(DT->getRootNode());
}

1
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -79,7 +79,6 @@ getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(ARM::SP);
Reserved.set(ARM::PC);
Reserved.set(ARM::FPSCR);
if (TFI->hasFP(MF))
Reserved.set(FramePtr);
if (hasBasePointer(MF))