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Convert DOUT to DEBUG(errs()...).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2009-08-22 20:30:53 +00:00
parent 1e973aae79
commit c3115a02c5
1 changed files with 67 additions and 55 deletions
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122
lib/CodeGen/RegAllocLinearScan.cpp
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@ -33,9 +33,8 @@
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include <algorithm> #include <algorithm>
@ -299,15 +298,20 @@ namespace {
template <typename ItTy> template <typename ItTy>
void printIntervals(const char* const str, ItTy i, ItTy e) const { void printIntervals(const char* const str, ItTy i, ItTy e) const {
if (str) DOUT << str << " intervals:\n"; DEBUG({
for (; i != e; ++i) { if (str)
DOUT << "\t" << *i->first << " -> "; errs() << str << " intervals:\n";
unsigned reg = i->first->reg;
if (TargetRegisterInfo::isVirtualRegister(reg)) { for (; i != e; ++i) {
reg = vrm_->getPhys(reg); errs() << "\t" << *i->first << " -> ";
}
DOUT << tri_->getName(reg) << '\n'; unsigned reg = i->first->reg;
} if (TargetRegisterInfo::isVirtualRegister(reg))
reg = vrm_->getPhys(reg);
errs() << tri_->getName(reg) << '\n';
}
});
} }
}; };
char RALinScan::ID = 0; char RALinScan::ID = 0;
@ -384,8 +388,8 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
// Try to coalesce. // Try to coalesce.
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) { if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg) DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
<< '\n'; << '\n');
vrm_->clearVirt(cur.reg); vrm_->clearVirt(cur.reg);
vrm_->assignVirt2Phys(cur.reg, PhysReg); vrm_->assignVirt2Phys(cur.reg, PhysReg);
@ -482,21 +486,21 @@ void RALinScan::initIntervalSets()
} }
} }
void RALinScan::linearScan() void RALinScan::linearScan() {
{
// linear scan algorithm // linear scan algorithm
DOUT << "********** LINEAR SCAN **********\n"; DEBUG({
DEBUG(errs() << "********** Function: " errs() << "********** LINEAR SCAN **********\n"
<< mf_->getFunction()->getName() << '\n'); << "********** Function: "
<< mf_->getFunction()->getName() << '\n';
DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end())); printIntervals("fixed", fixed_.begin(), fixed_.end());
});
while (!unhandled_.empty()) { while (!unhandled_.empty()) {
// pick the interval with the earliest start point // pick the interval with the earliest start point
LiveInterval* cur = unhandled_.top(); LiveInterval* cur = unhandled_.top();
unhandled_.pop(); unhandled_.pop();
++NumIters; ++NumIters;
DOUT << "\n*** CURRENT ***: " << *cur << '\n'; DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
if (!cur->empty()) { if (!cur->empty()) {
processActiveIntervals(cur->beginNumber()); processActiveIntervals(cur->beginNumber());
@ -511,15 +515,17 @@ void RALinScan::linearScan()
// assign it one. // assign it one.
assignRegOrStackSlotAtInterval(cur); assignRegOrStackSlotAtInterval(cur);
DEBUG(printIntervals("active", active_.begin(), active_.end())); DEBUG({
DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end())); printIntervals("active", active_.begin(), active_.end());
printIntervals("inactive", inactive_.begin(), inactive_.end());
});
} }
// Expire any remaining active intervals // Expire any remaining active intervals
while (!active_.empty()) { while (!active_.empty()) {
IntervalPtr &IP = active_.back(); IntervalPtr &IP = active_.back();
unsigned reg = IP.first->reg; unsigned reg = IP.first->reg;
DOUT << "\tinterval " << *IP.first << " expired\n"; DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) && assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
reg = vrm_->getPhys(reg); reg = vrm_->getPhys(reg);
@ -528,9 +534,11 @@ void RALinScan::linearScan()
} }
// Expire any remaining inactive intervals // Expire any remaining inactive intervals
DEBUG(for (IntervalPtrs::reverse_iterator DEBUG({
i = inactive_.rbegin(); i != inactive_.rend(); ++i) for (IntervalPtrs::reverse_iterator
DOUT << "\tinterval " << *i->first << " expired\n"); i = inactive_.rbegin(); i != inactive_.rend(); ++i)
errs() << "\tinterval " << *i->first << " expired\n";
});
inactive_.clear(); inactive_.clear();
// Add live-ins to every BB except for entry. Also perform trivial coalescing. // Add live-ins to every BB except for entry. Also perform trivial coalescing.
@ -565,7 +573,7 @@ void RALinScan::linearScan()
} }
} }
DOUT << *vrm_; DEBUG(errs() << *vrm_);
// Look for physical registers that end up not being allocated even though // Look for physical registers that end up not being allocated even though
// register allocator had to spill other registers in its register class. // register allocator had to spill other registers in its register class.
@ -579,7 +587,7 @@ void RALinScan::linearScan()
/// to the inactive list. /// to the inactive list.
void RALinScan::processActiveIntervals(unsigned CurPoint) void RALinScan::processActiveIntervals(unsigned CurPoint)
{ {
DOUT << "\tprocessing active intervals:\n"; DEBUG(errs() << "\tprocessing active intervals:\n");
for (unsigned i = 0, e = active_.size(); i != e; ++i) { for (unsigned i = 0, e = active_.size(); i != e; ++i) {
LiveInterval *Interval = active_[i].first; LiveInterval *Interval = active_[i].first;
@ -589,7 +597,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint); IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // Remove expired intervals. if (IntervalPos == Interval->end()) { // Remove expired intervals.
DOUT << "\t\tinterval " << *Interval << " expired\n"; DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) && assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
reg = vrm_->getPhys(reg); reg = vrm_->getPhys(reg);
@ -602,7 +610,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
} else if (IntervalPos->start > CurPoint) { } else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list. // Move inactive intervals to inactive list.
DOUT << "\t\tinterval " << *Interval << " inactive\n"; DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) && assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
reg = vrm_->getPhys(reg); reg = vrm_->getPhys(reg);
@ -625,7 +633,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint)
/// ones to the active list. /// ones to the active list.
void RALinScan::processInactiveIntervals(unsigned CurPoint) void RALinScan::processInactiveIntervals(unsigned CurPoint)
{ {
DOUT << "\tprocessing inactive intervals:\n"; DEBUG(errs() << "\tprocessing inactive intervals:\n");
for (unsigned i = 0, e = inactive_.size(); i != e; ++i) { for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
LiveInterval *Interval = inactive_[i].first; LiveInterval *Interval = inactive_[i].first;
@ -635,7 +643,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint)
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint); IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
if (IntervalPos == Interval->end()) { // remove expired intervals. if (IntervalPos == Interval->end()) { // remove expired intervals.
DOUT << "\t\tinterval " << *Interval << " expired\n"; DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
// Pop off the end of the list. // Pop off the end of the list.
inactive_[i] = inactive_.back(); inactive_[i] = inactive_.back();
@ -643,7 +651,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint)
--i; --e; --i; --e;
} else if (IntervalPos->start <= CurPoint) { } else if (IntervalPos->start <= CurPoint) {
// move re-activated intervals in active list // move re-activated intervals in active list
DOUT << "\t\tinterval " << *Interval << " active\n"; DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
assert(TargetRegisterInfo::isVirtualRegister(reg) && assert(TargetRegisterInfo::isVirtualRegister(reg) &&
"Can only allocate virtual registers!"); "Can only allocate virtual registers!");
reg = vrm_->getPhys(reg); reg = vrm_->getPhys(reg);
@ -769,10 +777,12 @@ void RALinScan::findIntervalsToSpill(LiveInterval *cur,
float Conflicts[3] = { 0.0f, 0.0f, 0.0f }; float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
SmallVector<LiveInterval*, 8> SLIs[3]; SmallVector<LiveInterval*, 8> SLIs[3];
DOUT << "\tConsidering " << NumCands << " candidates: "; DEBUG({
DEBUG(for (unsigned i = 0; i != NumCands; ++i) errs() << "\tConsidering " << NumCands << " candidates: ";
DOUT << tri_->getName(Candidates[i].first) << " "; for (unsigned i = 0; i != NumCands; ++i)
DOUT << "\n";); errs() << tri_->getName(Candidates[i].first) << " ";
errs() << "\n";
});
// Calculate the number of conflicts of each candidate. // Calculate the number of conflicts of each candidate.
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
@ -877,9 +887,8 @@ namespace {
/// assignRegOrStackSlotAtInterval - assign a register if one is available, or /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
/// spill. /// spill.
void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
{ DEBUG(errs() << "\tallocating current interval: ");
DOUT << "\tallocating current interval: ";
// This is an implicitly defined live interval, just assign any register. // This is an implicitly defined live interval, just assign any register.
const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
@ -887,7 +896,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
unsigned physReg = vrm_->getRegAllocPref(cur->reg); unsigned physReg = vrm_->getRegAllocPref(cur->reg);
if (!physReg) if (!physReg)
physReg = *RC->allocation_order_begin(*mf_); physReg = *RC->allocation_order_begin(*mf_);
DOUT << tri_->getName(physReg) << '\n'; DEBUG(errs() << tri_->getName(physReg) << '\n');
// Note the register is not really in use. // Note the register is not really in use.
vrm_->assignVirt2Phys(cur->reg, physReg); vrm_->assignVirt2Phys(cur->reg, physReg);
return; return;
@ -1020,7 +1029,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// the free physical register and add this interval to the active // the free physical register and add this interval to the active
// list. // list.
if (physReg) { if (physReg) {
DOUT << tri_->getName(physReg) << '\n'; DEBUG(errs() << tri_->getName(physReg) << '\n');
vrm_->assignVirt2Phys(cur->reg, physReg); vrm_->assignVirt2Phys(cur->reg, physReg);
addRegUse(physReg); addRegUse(physReg);
active_.push_back(std::make_pair(cur, cur->begin())); active_.push_back(std::make_pair(cur, cur->begin()));
@ -1036,7 +1045,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
} }
return; return;
} }
DOUT << "no free registers\n"; DEBUG(errs() << "no free registers\n");
// Compile the spill weights into an array that is better for scanning. // Compile the spill weights into an array that is better for scanning.
std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f); std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
@ -1054,7 +1063,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
updateSpillWeights(SpillWeights, reg, i->first->weight, RC); updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
} }
DOUT << "\tassigning stack slot at interval "<< *cur << ":\n"; DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
// Find a register to spill. // Find a register to spill.
float minWeight = HUGE_VALF; float minWeight = HUGE_VALF;
@ -1121,16 +1130,19 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
--LastCandidate; --LastCandidate;
} }
DOUT << "\t\tregister(s) with min weight(s): "; DEBUG({
DEBUG(for (unsigned i = 0; i != LastCandidate; ++i) errs() << "\t\tregister(s) with min weight(s): ";
DOUT << tri_->getName(RegsWeights[i].first)
<< " (" << RegsWeights[i].second << ")\n"); for (unsigned i = 0; i != LastCandidate; ++i)
errs() << tri_->getName(RegsWeights[i].first)
<< " (" << RegsWeights[i].second << ")\n";
});
// If the current has the minimum weight, we need to spill it and // If the current has the minimum weight, we need to spill it and
// add any added intervals back to unhandled, and restart // add any added intervals back to unhandled, and restart
// linearscan. // linearscan.
if (cur->weight != HUGE_VALF && cur->weight <= minWeight) { if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
DOUT << "\t\t\tspilling(c): " << *cur << '\n'; DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
SmallVector<LiveInterval*, 8> spillIs; SmallVector<LiveInterval*, 8> spillIs;
std::vector<LiveInterval*> added; std::vector<LiveInterval*> added;
@ -1212,7 +1224,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
while (!spillIs.empty()) { while (!spillIs.empty()) {
LiveInterval *sli = spillIs.back(); LiveInterval *sli = spillIs.back();
spillIs.pop_back(); spillIs.pop_back();
DOUT << "\t\t\tspilling(a): " << *sli << '\n'; DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
earliestStartInterval = earliestStartInterval =
(earliestStartInterval->beginNumber() < sli->beginNumber()) ? (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
earliestStartInterval : sli; earliestStartInterval : sli;
@ -1230,7 +1242,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
unsigned earliestStart = earliestStartInterval->beginNumber(); unsigned earliestStart = earliestStartInterval->beginNumber();
DOUT << "\t\trolling back to: " << earliestStart << '\n'; DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
// Scan handled in reverse order up to the earliest start of a // Scan handled in reverse order up to the earliest start of a
// spilled live interval and undo each one, restoring the state of // spilled live interval and undo each one, restoring the state of
@ -1240,7 +1252,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
// If this interval starts before t we are done. // If this interval starts before t we are done.
if (i->beginNumber() < earliestStart) if (i->beginNumber() < earliestStart)
break; break;
DOUT << "\t\t\tundo changes for: " << *i << '\n'; DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
handled_.pop_back(); handled_.pop_back();
// When undoing a live interval allocation we must know if it is active or // When undoing a live interval allocation we must know if it is active or
@ -1290,7 +1302,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
LiveInterval *HI = handled_[i]; LiveInterval *HI = handled_[i];
if (!HI->expiredAt(earliestStart) && if (!HI->expiredAt(earliestStart) &&
HI->expiredAt(cur->beginNumber())) { HI->expiredAt(cur->beginNumber())) {
DOUT << "\t\t\tundo changes for: " << *HI << '\n'; DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
active_.push_back(std::make_pair(HI, HI->begin())); active_.push_back(std::make_pair(HI, HI->begin()));
assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg)); assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
addRegUse(vrm_->getPhys(HI->reg)); addRegUse(vrm_->getPhys(HI->reg));
@ -1419,7 +1431,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
// available first. // available first.
unsigned Preference = vrm_->getRegAllocPref(cur->reg); unsigned Preference = vrm_->getRegAllocPref(cur->reg);
if (Preference) { if (Preference) {
DOUT << "(preferred: " << tri_->getName(Preference) << ") "; DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
if (isRegAvail(Preference) && if (isRegAvail(Preference) &&
RC->contains(Preference)) RC->contains(Preference))
return Preference; return Preference;