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Remove uses of MachineOperand::isVirtualRegister

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11281 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-10 20:55:47 +00:00
parent ebcd7941f0
commit c31ecb9aae
2 changed files with 12 additions and 6 deletions
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9
lib/Target/X86/PeepholeOptimizer.cpp
View File

@@ -191,7 +191,8 @@ namespace {
MachineInstr *MI = *I; MachineInstr *MI = *I;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse()) if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
setDefinition(MO.getReg(), MI); setDefinition(MO.getReg(), MI);
} }
} }
@@ -250,7 +251,8 @@ namespace {
/// register, return the machine instruction defining it, otherwise, return /// register, return the machine instruction defining it, otherwise, return
/// null. /// null.
MachineInstr *getDefiningInst(MachineOperand &MO) { MachineInstr *getDefiningInst(MachineOperand &MO) {
if (MO.isDef() || !MO.isVirtualRegister()) return 0; if (MO.isDef() || !MO.isRegister() ||
!MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
return UDC->getDefinition(MO.getReg()); return UDC->getDefinition(MO.getReg());
} }
@@ -391,7 +393,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
DefInst->getOpcode() == X86::MOVrr32) { DefInst->getOpcode() == X86::MOVrr32) {
// Don't propagate physical registers into PHI nodes... // Don't propagate physical registers into PHI nodes...
if (MI->getOpcode() != X86::PHI || if (MI->getOpcode() != X86::PHI ||
DefInst->getOperand(1).isVirtualRegister()) (DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg())))
Changed = Propagate(MI, i, DefInst, 1); Changed = Propagate(MI, i, DefInst, 1);
} }

9
lib/Target/X86/X86PeepholeOpt.cpp
View File

@@ -191,7 +191,8 @@ namespace {
MachineInstr *MI = *I; MachineInstr *MI = *I;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse()) if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
setDefinition(MO.getReg(), MI); setDefinition(MO.getReg(), MI);
} }
} }
@@ -250,7 +251,8 @@ namespace {
/// register, return the machine instruction defining it, otherwise, return /// register, return the machine instruction defining it, otherwise, return
/// null. /// null.
MachineInstr *getDefiningInst(MachineOperand &MO) { MachineInstr *getDefiningInst(MachineOperand &MO) {
if (MO.isDef() || !MO.isVirtualRegister()) return 0; if (MO.isDef() || !MO.isRegister() ||
!MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
return UDC->getDefinition(MO.getReg()); return UDC->getDefinition(MO.getReg());
} }
@@ -391,7 +393,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
DefInst->getOpcode() == X86::MOVrr32) { DefInst->getOpcode() == X86::MOVrr32) {
// Don't propagate physical registers into PHI nodes... // Don't propagate physical registers into PHI nodes...
if (MI->getOpcode() != X86::PHI || if (MI->getOpcode() != X86::PHI ||
DefInst->getOperand(1).isVirtualRegister()) (DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg())))
Changed = Propagate(MI, i, DefInst, 1); Changed = Propagate(MI, i, DefInst, 1);
} }