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A7.3 register encoding

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Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-05 22:57:07 +00:00
parent da19475328
commit c3281c10c9
3 changed files with 21 additions and 1 deletions
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10
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -94,6 +94,16 @@ getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
}
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
// A7.3 register encoding
// Qd -> bit[12] == 0
// Qn -> bit[16] == 0
// Qm -> bit[0] == 0
//
// If one of these bits is 1, the instruction is UNDEFINED.
if (RegClassID == ARM::QPRRegClassID && slice(RawRegister, 0, 0) == 1) {
B->SetErr(-1);
return 0;
}
unsigned RegNum =
RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;

10
test/MC/Disassembler/ARM/invalid-VQADD-arm.txt Normal file
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@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# Qm -> bit[0] == 0, otherwise UNDEFINED
0xdb 0xe0 0x40 0xf2

2
test/MC/Disassembler/ARM/neon-tests.txt
View File

@ -67,7 +67,7 @@
0x5f 0xe5 0xc4 0xf2
# CHECK: vbic.i32 q2, #0xA900
0x79 0x53 0x82 0xf3
0x79 0x43 0x82 0xf3
# CHECK: vst2.32 {d16, d18}, [r2, :64], r2
0x92 0x9 0x42 0xf4