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All targets expand BR_JT for now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-10-30 08:02:39 +00:00
parent 3d4ce11085
commit c35497fc2a
6 changed files with 11 additions and 4 deletions
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3
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -73,7 +73,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::BRIND, MVT::i32, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
setOperationAction(ISD::BR_CC, MVT::f64, Custom);

3
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -62,7 +62,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setStoreXAction(MVT::i1, Promote);
// setOperationAction(ISD::BRIND, MVT::i64, Expand);
// setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

3
lib/Target/IA64/IA64ISelLowering.cpp
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@ -44,7 +44,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
setOperationAction(ISD::BRIND , MVT::i64, Expand);
setOperationAction(ISD::BRIND , MVT::Other, Expand);
setOperationAction(ISD::BR_JT , MVT::Other, Expand);
setOperationAction(ISD::BR_CC , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);

2
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -107,6 +107,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// PowerPC does not have BRCOND which requires SetCC
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);

3
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -174,7 +174,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
// Sparc doesn't have BRCOND either, it has BR_CC.
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BRIND, MVT::i32, Expand);
setOperationAction(ISD::BRIND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
setOperationAction(ISD::BR_CC, MVT::f64, Custom);

1
lib/Target/X86/X86ISelLowering.cpp
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@ -146,6 +146,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
setOperationAction(ISD::BR_JT , MVT::Other, Expand);
setOperationAction(ISD::BRCOND , MVT::Other, Custom);
setOperationAction(ISD::BR_CC , MVT::Other, Expand);
setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);