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[mips][microMIPS] Implement CodeGen support for LI16 instruction.

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Differential Revision: http://reviews.llvm.org/D5840


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek 2014-12-11 13:56:23 +00:00
parent c57bee5399
commit c3692e5c67
4 changed files with 31 additions and 5 deletions
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14
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -261,8 +261,7 @@ class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
let isReMaterializable = 1;
}
class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
SDPatternOperator imm_type = null_frag> :
class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
let isReMaterializable = 1;
@ -440,8 +439,8 @@ def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>,
LI_FM_MM16, IsAsCheapAsAMove;
def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
@ -686,6 +685,13 @@ let Predicates = [InMicroMips] in {
// MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
def : MipsPat<(i32 immLi16:$imm),
(LI16_MM immLi16:$imm)>;
def : MipsPat<(i32 immSExt16:$imm),
(ADDiu_MM ZERO, immSExt16:$imm)>;
def : MipsPat<(i32 immZExt16:$imm),
(ORi_MM ZERO, immZExt16:$imm)>;
def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
(ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),

2
lib/Target/Mips/MipsInstrInfo.td
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@ -1654,10 +1654,12 @@ class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
// Small immediates
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 immSExt16:$in),
(ADDiu ZERO, imm:$in)>;
def : MipsPat<(i32 immZExt16:$in),
(ORi ZERO, imm:$in)>;
}
def : MipsPat<(i32 immLow16Zero:$in),
(LUi (HI16 imm:$in))>;

2
test/CodeGen/Mips/longbranch.ll
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@ -123,7 +123,7 @@ end:
; MICROMIPS: $[[BB0]]:
; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; MICROMIPS: addiu $[[R2:[0-9]+]], $zero, 1
; MICROMIPS: li16 $[[R2:[0-9]+]], 1
; MICROMIPS: sw $[[R2]], 0($[[R1]])
; MICROMIPS: $[[BB2]]:
; MICROMIPS: jr $ra

18
test/CodeGen/Mips/micromips-li.ll Normal file
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@ -0,0 +1,18 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = external global i32
@y = external global i32
@z = external global i32
define i32 @main() nounwind {
entry:
store i32 1, i32* @x, align 4
store i32 2148, i32* @y, align 4
store i32 33332, i32* @z, align 4
ret i32 0
}
; CHECK: li16 ${{[2-7]|16|17}}, 1
; CHECK: addiu ${{[0-9]+}}, $zero, 2148
; CHECK: ori ${{[0-9]+}}, $zero, 33332