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[X86] Add IntrNoMem to the AVX512 conflict intrinsics.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2015-01-23 06:11:45 +00:00
parent eb3eb88fb7
commit c3942c9623
2 changed files with 13 additions and 5 deletions
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8
include/llvm/IR/IntrinsicsX86.td
View File

@ -3404,22 +3404,22 @@ let TargetPrefix = "x86" in {
GCCBuiltin<"__builtin_ia32_vpconflictsi_512_mask">, GCCBuiltin<"__builtin_ia32_vpconflictsi_512_mask">,
Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
llvm_v16i32_ty, llvm_i16_ty], llvm_v16i32_ty, llvm_i16_ty],
[]>; [IntrNoMem]>;
def int_x86_avx512_mask_conflict_q_512 : def int_x86_avx512_mask_conflict_q_512 :
GCCBuiltin<"__builtin_ia32_vpconflictdi_512_mask">, GCCBuiltin<"__builtin_ia32_vpconflictdi_512_mask">,
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
llvm_v8i64_ty, llvm_i8_ty], llvm_v8i64_ty, llvm_i8_ty],
[]>; [IntrNoMem]>;
def int_x86_avx512_mask_lzcnt_d_512 : def int_x86_avx512_mask_lzcnt_d_512 :
GCCBuiltin<"__builtin_ia32_vplzcntd_512_mask">, GCCBuiltin<"__builtin_ia32_vplzcntd_512_mask">,
Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
llvm_v16i32_ty, llvm_i16_ty], llvm_v16i32_ty, llvm_i16_ty],
[]>; [IntrNoMem]>;
def int_x86_avx512_mask_lzcnt_q_512 : def int_x86_avx512_mask_lzcnt_q_512 :
GCCBuiltin<"__builtin_ia32_vplzcntq_512_mask">, GCCBuiltin<"__builtin_ia32_vplzcntq_512_mask">,
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
llvm_v8i64_ty, llvm_i8_ty], llvm_v8i64_ty, llvm_i8_ty],
[]>; [IntrNoMem]>;
} }
// Vector blend // Vector blend

8
lib/Target/X86/X86InstrAVX512.td
View File

@ -5083,14 +5083,17 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
RegisterClass RC, RegisterClass KRC, RegisterClass RC, RegisterClass KRC,
X86MemOperand x86memop, X86MemOperand x86memop,
X86MemOperand x86scalar_mop, string BrdcstStr> { X86MemOperand x86scalar_mop, string BrdcstStr> {
let hasSideEffects = 0 in {
def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src), (ins RC:$src),
!strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"), !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
[]>, EVEX; []>, EVEX;
let mayLoad = 1 in
def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins x86memop:$src), (ins x86memop:$src),
!strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"), !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
[]>, EVEX; []>, EVEX;
let mayLoad = 1 in
def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins x86scalar_mop:$src), (ins x86scalar_mop:$src),
!strconcat(OpcodeStr, "\t{${src}", BrdcstStr, !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
@ -5101,11 +5104,13 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
[]>, EVEX, EVEX_KZ; []>, EVEX, EVEX_KZ;
let mayLoad = 1 in
def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins KRC:$mask, x86memop:$src), (ins KRC:$mask, x86memop:$src),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
[]>, EVEX, EVEX_KZ; []>, EVEX, EVEX_KZ;
let mayLoad = 1 in
def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins KRC:$mask, x86scalar_mop:$src), (ins KRC:$mask, x86scalar_mop:$src),
!strconcat(OpcodeStr, "\t{${src}", BrdcstStr, !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
@ -5119,17 +5124,20 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
[]>, EVEX, EVEX_K; []>, EVEX, EVEX_K;
let mayLoad = 1 in
def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, KRC:$mask, x86memop:$src2), (ins RC:$src1, KRC:$mask, x86memop:$src2),
!strconcat(OpcodeStr, !strconcat(OpcodeStr,
"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
[]>, EVEX, EVEX_K; []>, EVEX, EVEX_K;
let mayLoad = 1 in
def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, KRC:$mask, x86scalar_mop:$src2), (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
!strconcat(OpcodeStr, "\t{${src2}", BrdcstStr, !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"), ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
[]>, EVEX, EVEX_K, EVEX_B; []>, EVEX, EVEX_K, EVEX_B;
} }
}
} }
let Predicates = [HasCDI] in { let Predicates = [HasCDI] in {