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[AArch64] Add support for NEON scalar extract narrow instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2013-10-18 14:03:24 +00:00
parent e1bc6ddc0b
commit c439c205ba
5 changed files with 277 additions and 0 deletions
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48
lib/Target/AArch64/AArch64InstrNEON.td
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@@ -3292,6 +3292,22 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
[], NoItinerary>;
}
multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
string asmop> {
def bh : NeonI_Scalar2SameMisc<u, 0b00, opcode,
(outs FPR8:$Rd), (ins FPR16:$Rn),
!strconcat(asmop, " $Rd, $Rn"),
[], NoItinerary>;
def hs : NeonI_Scalar2SameMisc<u, 0b01, opcode,
(outs FPR16:$Rd), (ins FPR32:$Rn),
!strconcat(asmop, " $Rd, $Rn"),
[], NoItinerary>;
def sd : NeonI_Scalar2SameMisc<u, 0b10, opcode,
(outs FPR32:$Rd), (ins FPR64:$Rn),
!strconcat(asmop, " $Rd, $Rn"),
[], NoItinerary>;
}
multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
string asmop> {
@@ -3366,6 +3382,20 @@ multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
(INSTS FPR32:$Rn)>;
}
multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
SDPatternOperator opnode,
Instruction INSTH,
Instruction INSTS,
Instruction INSTD> {
def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
(INSTH FPR16:$Rn)>;
def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
(INSTS FPR32:$Rn)>;
def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
(INSTD FPR64:$Rn)>;
}
multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
SDPatternOperator opnode,
Instruction INSTB,
@@ -3645,6 +3675,24 @@ defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
USQADDbb, USQADDhh,
USQADDss, USQADDdd>;
// Scalar Signed Saturating Extract Unsigned Narrow
defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
SQXTUNbh, SQXTUNhs,
SQXTUNsd>;
// Scalar Signed Saturating Extract Narrow
defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
SQXTNbh, SQXTNhs,
SQXTNsd>;
// Scalar Unsigned Saturating Extract Narrow
defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
UQXTNbh, UQXTNhs,
UQXTNsd>;
// Scalar Reduce Pairwise
multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,