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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jia Liu
2012-02-27 02:21:34 +00:00
parent 23b6ec906a
commit c4a238c20f
1 changed files with 14 additions and 16 deletions
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4
lib/Target/Mips/MipsRegisterInfo.td
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@@ -1,4 +1,4 @@
//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@@ -69,8 +69,6 @@ class HWR<bits<5> num, string n> : MipsReg<n> {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Namespace = "Mips" in { let Namespace = "Mips" in {
// FIXME: Fix DwarfRegNum.
// General Purpose Registers // General Purpose Registers
def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;