Added getTargetLowering() to TargetMachine. Refactored targets to support this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/IA64/IA64.h

@@ -18,26 +18,26 @@
 
 namespace llvm {
 
-class TargetMachine;
+class IA64TargetMachine;
 class FunctionPass;
 class IntrinsicLowering;
 
 /// createIA64DAGToDAGInstructionSelector - This pass converts an LLVM
 /// function into IA64 machine code in a sane, DAG->DAG transform.
 ///
-FunctionPass *createIA64DAGToDAGInstructionSelector(TargetMachine &TM);
+FunctionPass *createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM);
 
 /// createIA64BundlingPass - This pass adds stop bits and bundles
 /// instructions.
 ///
-FunctionPass *createIA64BundlingPass(TargetMachine &TM);
+FunctionPass *createIA64BundlingPass(IA64TargetMachine &TM);
 
 /// createIA64CodePrinterPass - Returns a pass that prints the IA64
 /// assembly code for a MachineFunction to the given output stream,
 /// using the given target machine description.  This should work
 /// regardless of whether the function is in SSA form.
 ///
-FunctionPass *createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm);
+FunctionPass *createIA64CodePrinterPass(std::ostream &o, IA64TargetMachine &tm);
 
 } // End llvm namespace
 

lib/Target/IA64/IA64AsmPrinter.cpp

@@ -374,7 +374,8 @@ bool IA64AsmPrinter::doFinalization(Module &M) {
 /// assembly code for a MachineFunction to the given output stream, using
 /// the given target machine description.
 ///
-FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,TargetMachine &tm){
+FunctionPass *llvm::createIA64CodePrinterPass(std::ostream &o,
+                                              IA64TargetMachine &tm) {
   return new IA64AsmPrinter(o, tm);
 }
 

lib/Target/IA64/IA64Bundling.cpp

@@ -37,9 +37,9 @@ namespace {
     /// Target machine description which we query for reg. names, data
     /// layout, etc.
     ///
-    TargetMachine &TM;
+    IA64TargetMachine &TM;
 
-    IA64BundlingPass(TargetMachine &tm) : TM(tm) { }
+    IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }
 
     virtual const char *getPassName() const {
       return "IA64 (Itanium) Bundling Pass";
@@ -64,7 +64,7 @@ namespace {
 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
 /// and arranges the result into bundles.
 ///
-FunctionPass *llvm::createIA64BundlingPass(TargetMachine &tm) {
+FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
   return new IA64BundlingPass(tm);
 }
 

lib/Target/IA64/IA64ISelDAGToDAG.cpp

@@ -42,8 +42,8 @@ namespace {
     IA64TargetLowering IA64Lowering;
     unsigned GlobalBaseReg;
   public:
-    IA64DAGToDAGISel(TargetMachine &TM)
+    IA64DAGToDAGISel(IA64TargetMachine &TM)
-      : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
+      : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
     
     virtual bool runOnFunction(Function &Fn) {
       // Make sure we re-emit a set of the global base reg if necessary
@@ -621,7 +621,8 @@ void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
 /// into an IA64-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
+FunctionPass
+*llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
   return new IA64DAGToDAGISel(TM);
 }
 

lib/Target/IA64/IA64TargetMachine.cpp

@@ -79,7 +79,8 @@ unsigned IA64TargetMachine::getModuleMatchQuality(const Module &M) {
 IA64TargetMachine::IA64TargetMachine(const Module &M, IntrinsicLowering *IL,
                                      const std::string &FS)
   : TargetMachine("IA64", IL, true),
-    FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0) { // FIXME? check this stuff
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
+    TLInfo(*this) { // FIXME? check this stuff
 }
 
 // addPassesToEmitFile - We currently use all of the same passes as the JIT

lib/Target/IA64/IA64TargetMachine.h

@@ -18,20 +18,23 @@
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/PassManager.h"
 #include "IA64InstrInfo.h"
+#include "IA64ISelLowering.h"
 
 namespace llvm {
 class IntrinsicLowering;
 
 class IA64TargetMachine : public TargetMachine {
-  IA64InstrInfo    InstrInfo;
+  IA64InstrInfo      InstrInfo;
-  TargetFrameInfo FrameInfo;
+  TargetFrameInfo    FrameInfo;
   //IA64JITInfo      JITInfo;
+  IA64TargetLowering TLInfo;
 public:
   IA64TargetMachine(const Module &M, IntrinsicLowering *IL,
                     const std::string &FS);
 
-  virtual const IA64InstrInfo     *getInstrInfo() const { return &InstrInfo; }
+  virtual const IA64InstrInfo      *getInstrInfo() const { return &InstrInfo; }
-  virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
+  virtual const TargetFrameInfo    *getFrameInfo() const { return &FrameInfo; }
+  virtual       IA64TargetLowering *getTargetLowering()  { return &TLInfo; }
   virtual const MRegisterInfo    *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }

lib/Target/PowerPC/PPC.h

@@ -20,16 +20,16 @@
 namespace llvm {
 
 class FunctionPass;
-class TargetMachine;
+class PPCTargetMachine;
 
 enum PPCTargetEnum {
   TargetDefault, TargetAIX, TargetDarwin
 };
 
 FunctionPass *createPPCBranchSelectionPass();
-FunctionPass *createPPCISelDag(TargetMachine &TM);
+FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
-FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
+FunctionPass *createDarwinAsmPrinter(std::ostream &OS, PPCTargetMachine &TM);
-FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
+FunctionPass *createAIXAsmPrinter(std::ostream &OS, PPCTargetMachine &TM);
 
 extern PPCTargetEnum PPCTarget;
 } // end namespace llvm;

lib/Target/PowerPC/PPCAsmPrinter.cpp

@@ -307,7 +307,8 @@ namespace {
 /// code for a MachineFunction to the given output stream, in a format that the
 /// Darwin assembler can deal with.
 ///
-FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
+FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o,
+                                           PPCTargetMachine &tm) {
   return new DarwinAsmPrinter(o, tm);
 }
 
@@ -315,7 +316,7 @@ FunctionPass *llvm::createDarwinAsmPrinter(std::ostream &o, TargetMachine &tm) {
 /// for a MachineFunction to the given output stream, in a format that the
 /// AIX 5L assembler can deal with.
 ///
-FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, TargetMachine &tm) {
+FunctionPass *llvm::createAIXAsmPrinter(std::ostream &o, PPCTargetMachine &tm) {
   return new AIXAsmPrinter(o, tm);
 }
 

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

@@ -42,8 +42,9 @@ namespace {
     PPCTargetLowering PPCLowering;
     unsigned GlobalBaseReg;
   public:
-    PPCDAGToDAGISel(TargetMachine &TM)
+    PPCDAGToDAGISel(PPCTargetMachine &TM)
-      : SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
+      : SelectionDAGISel(PPCLowering),
+        PPCLowering(*TM.getTargetLowering()){}
     
     virtual bool runOnFunction(Function &Fn) {
       // Make sure we re-emit a set of the global base reg if necessary
@@ -1140,7 +1141,7 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 /// createPPCISelDag - This pass converts a legalized DAG into a 
 /// PowerPC-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
   return new PPCDAGToDAGISel(TM);
 }
 

lib/Target/PowerPC/PPCISelLowering.cpp

@@ -14,6 +14,7 @@
 #include "PPCISelLowering.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/VectorExtras.h"
+#include "llvm/Analysis/ScalarEvolutionExpressions.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -1174,3 +1175,10 @@ isOperandValidForConstraint(SDOperand Op, char Letter) {
   // Handle standard constraint letters.
   return TargetLowering::isOperandValidForConstraint(Op, Letter);
 }
+
+/// isLegalAddressImmediate - Return true if the integer value can be used
+/// as the offset of the target addressing mode.
+bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
+  // PPC allows a sign-extended 16-bit immediate field.
+  return (V > -(1 << 16) && V < (1 << 16)-1);
+}

lib/Target/PowerPC/PPCISelLowering.h

@@ -109,6 +109,10 @@ namespace llvm {
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
     bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
+
+    /// isLegalAddressImmediate - Return true if the integer value can be used
+    /// as the offset of the target addressing mode.
+    virtual bool isLegalAddressImmediate(int64_t V) const;
   };
 }
 

lib/Target/PowerPC/PPCJITInfo.h

@@ -17,13 +17,13 @@
 #include "llvm/Target/TargetJITInfo.h"
 
 namespace llvm {
-  class TargetMachine;
+  class PPCTargetMachine;
 
   class PPCJITInfo : public TargetJITInfo {
   protected:
-    TargetMachine &TM;
+    PPCTargetMachine &TM;
   public:
-    PPCJITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;}
+    PPCJITInfo(PPCTargetMachine &tm) : TM(tm) {useGOT = 0;}
 
     /// addPassesToJITCompile - Add passes to the specified pass manager to
     /// implement a fast dynamic compiler for this target.  Return true if this

lib/Target/PowerPC/PPCTargetMachine.cpp

@@ -62,7 +62,7 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
                                    const std::string &FS)
 : TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
   Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
-  InstrItins(Subtarget.getInstrItineraryData()) {
+  TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) {
   if (TargetDefault == PPCTarget) {
     if (Subtarget.isAIX()) PPCTarget = TargetAIX;
     if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;

lib/Target/PowerPC/PPCTargetMachine.h

@@ -18,6 +18,7 @@
 #include "PPCSubtarget.h"
 #include "PPCJITInfo.h"
 #include "PPCInstrInfo.h"
+#include "PPCISelLowering.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
@@ -31,6 +32,7 @@ class PPCTargetMachine : public TargetMachine {
   PPCSubtarget           Subtarget;
   PPCFrameInfo           FrameInfo;
   PPCJITInfo             JITInfo;
+  PPCTargetLowering      TLInfo;
   InstrItineraryData     InstrItins;
 public:
   PPCTargetMachine(const Module &M, IntrinsicLowering *IL,
@@ -40,6 +42,7 @@ public:
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
   virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
   virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
+  virtual       PPCTargetLowering *getTargetLowering() { return &TLInfo; }
   virtual const MRegisterInfo    *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }

lib/Target/X86/X86.h

@@ -19,7 +19,7 @@
 
 namespace llvm {
 
-class TargetMachine;
+class X86TargetMachine;
 class PassManager;
 class FunctionPass;
 class IntrinsicLowering;
@@ -28,7 +28,7 @@ class MachineCodeEmitter;
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *createX86ISelDag(TargetMachine &TM);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
@@ -40,7 +40,7 @@ FunctionPass *createX86FloatingPointStackifierPass();
 /// assembly code for a MachineFunction to the given output stream,
 /// using the given target machine description.
 ///
-FunctionPass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm);
+FunctionPass *createX86CodePrinterPass(std::ostream &o, X86TargetMachine &tm);
 
 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
 /// to the specified MCE object.
@@ -50,7 +50,7 @@ FunctionPass *createX86CodeEmitterPass(MachineCodeEmitter &MCE);
 /// code as an ELF object file.
 ///
 void addX86ELFObjectWriterPass(PassManager &FPM,
-                               std::ostream &o, TargetMachine &tm);
+                               std::ostream &o, X86TargetMachine &tm);
 
 /// createX86EmitCodeToMemory - Returns a pass that converts a register
 /// allocated function into raw machine code in a dynamically

lib/Target/X86/X86ATTAsmPrinter.cpp

@@ -21,7 +21,6 @@
 #include "llvm/Target/TargetOptions.h"
 #include <iostream>
 using namespace llvm;
-using namespace x86;
 
 /// runOnMachineFunction - This uses the printMachineInstruction()
 /// method to print assembly for each instruction.

lib/Target/X86/X86ATTAsmPrinter.h

@@ -18,10 +18,9 @@
 #include "llvm/CodeGen/ValueTypes.h"
 
 namespace llvm {
-namespace x86 {
 
 struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
- X86ATTAsmPrinter(std::ostream &O, TargetMachine &TM)
+ X86ATTAsmPrinter(std::ostream &O, X86TargetMachine &TM)
     : X86SharedAsmPrinter(O, TM) { }
 
   virtual const char *getPassName() const {
@@ -69,7 +68,6 @@ struct X86ATTAsmPrinter : public X86SharedAsmPrinter {
   bool runOnMachineFunction(MachineFunction &F);
 };
 
-} // end namespace x86
 } // end namespace llvm
 
 #endif

lib/Target/X86/X86AsmPrinter.cpp

@@ -14,10 +14,10 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "X86AsmPrinter.h"
 #include "X86ATTAsmPrinter.h"
 #include "X86IntelAsmPrinter.h"
 #include "X86Subtarget.h"
-#include "X86.h"
 #include "llvm/Constants.h"
 #include "llvm/Module.h"
 #include "llvm/Type.h"
@@ -25,10 +25,9 @@
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
-using namespace x86;
 
-Statistic<> llvm::x86::EmittedInsts("asm-printer",
+Statistic<> llvm::EmittedInsts("asm-printer",
-                                    "Number of machine instrs printed");
+                               "Number of machine instrs printed");
 
 enum AsmWriterFlavorTy { att, intel };
 cl::opt<AsmWriterFlavorTy>
@@ -210,7 +209,8 @@ bool X86SharedAsmPrinter::doFinalization(Module &M) {
 /// for a MachineFunction to the given output stream, using the given target
 /// machine description.
 ///
-FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
+FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,
+                                             X86TargetMachine &tm){
   switch (AsmWriterFlavor) {
   default:
     assert(0 && "Unknown asm flavor!");

lib/Target/X86/X86AsmPrinter.h

@@ -17,6 +17,7 @@
 #define X86ASMPRINTER_H
 
 #include "X86.h"
+#include "X86TargetMachine.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/DwarfWriter.h"
 #include "llvm/CodeGen/MachineDebugInfo.h"
@@ -25,7 +26,6 @@
 
 
 namespace llvm {
-namespace x86 {
 
 extern Statistic<> EmittedInsts;
 
@@ -56,7 +56,7 @@ X86DwarfWriter(std::ostream &o, AsmPrinter *ap)
 struct X86SharedAsmPrinter : public AsmPrinter {
   X86DwarfWriter DW;
 
-  X86SharedAsmPrinter(std::ostream &O, TargetMachine &TM)
+  X86SharedAsmPrinter(std::ostream &O, X86TargetMachine &TM)
     : AsmPrinter(O, TM), DW(O, this), forDarwin(false) { }
 
   bool doInitialization(Module &M);
@@ -90,7 +90,6 @@ struct X86SharedAsmPrinter : public AsmPrinter {
   }
 };
 
-} // end namespace x86
 } // end namespace llvm
 
 #endif

lib/Target/X86/X86ELFWriter.cpp

@@ -13,15 +13,15 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86.h"
+#include "X86TargetMachine.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/ELFWriter.h"
-#include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
 namespace {
   class X86ELFWriter : public ELFWriter {
   public:
-    X86ELFWriter(std::ostream &O, TargetMachine &TM) : ELFWriter(O, TM) {
+    X86ELFWriter(std::ostream &O, X86TargetMachine &TM) : ELFWriter(O, TM) {
       e_machine = 3;   // EM_386
     }
   };
@@ -31,7 +31,7 @@ namespace {
 /// as an ELF object file.
 ///
 void llvm::addX86ELFObjectWriterPass(PassManager &FPM,
-                                     std::ostream &O, TargetMachine &TM) {
+                                     std::ostream &O, X86TargetMachine &TM) {
   X86ELFWriter *EW = new X86ELFWriter(O, TM);
   FPM.add(EW);
   FPM.add(createX86CodeEmitterPass(EW->getMachineCodeEmitter()));

lib/Target/X86/X86ISelDAGToDAG.cpp

@@ -15,9 +15,10 @@
 #define DEBUG_TYPE "isel"
 #include "X86.h"
 #include "X86InstrBuilder.h"
+#include "X86ISelLowering.h"
 #include "X86RegisterInfo.h"
 #include "X86Subtarget.h"
-#include "X86ISelLowering.h"
+#include "X86TargetMachine.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Instructions.h"
 #include "llvm/Support/CFG.h"
@@ -90,8 +91,9 @@ namespace {
 
     unsigned GlobalBaseReg;
   public:
-    X86DAGToDAGISel(TargetMachine &TM)
+    X86DAGToDAGISel(X86TargetMachine &TM)
-      : SelectionDAGISel(X86Lowering), X86Lowering(TM) {
+      : SelectionDAGISel(X86Lowering),
+        X86Lowering(*TM.getTargetLowering()) {
       Subtarget = &TM.getSubtarget<X86Subtarget>();
     }
 
@@ -842,6 +844,6 @@ void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
 /// createX86ISelDag - This pass converts a legalized DAG into a 
 /// X86-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createX86ISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
   return new X86DAGToDAGISel(TM);
 }

lib/Target/X86/X86ISelLowering.h

@@ -230,6 +230,12 @@ namespace llvm {
     std::vector<unsigned> 
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
+
+    /// isLegalAddressImmediate - Return true if the integer value or
+    /// GlobalValue can be used as the offset of the target addressing mode.
+    virtual bool isLegalAddressImmediate(int64_t V) const;
+    virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
+
   private:
     // C Calling Convention implementation.
     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);

lib/Target/X86/X86IntelAsmPrinter.cpp

@@ -20,7 +20,6 @@
 #include "llvm/Support/Mangler.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
-using namespace x86;
 
 /// runOnMachineFunction - This uses the printMachineInstruction()
 /// method to print assembly for each instruction.

lib/Target/X86/X86IntelAsmPrinter.h

@@ -16,14 +16,12 @@
 
 #include "X86AsmPrinter.h"
 #include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MRegisterInfo.h"
 
 namespace llvm {
-namespace x86 {
 
 struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
- X86IntelAsmPrinter(std::ostream &O, TargetMachine &TM)
+ X86IntelAsmPrinter(std::ostream &O, X86TargetMachine &TM)
     : X86SharedAsmPrinter(O, TM) { }
 
   virtual const char *getPassName() const {
@@ -91,7 +89,6 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
   bool doInitialization(Module &M);
 };
 
-} // end namespace x86
 } // end namespace llvm
 
 #endif

lib/Target/X86/X86JITInfo.h

@@ -17,13 +17,13 @@
 #include "llvm/Target/TargetJITInfo.h"
 
 namespace llvm {
-  class TargetMachine;
+  class X86TargetMachine;
   class IntrinsicLowering;
 
   class X86JITInfo : public TargetJITInfo {
-    TargetMachine &TM;
+    X86TargetMachine &TM;
   public:
-    X86JITInfo(TargetMachine &tm) : TM(tm) {useGOT = 0;}
+    X86JITInfo(X86TargetMachine &tm) : TM(tm) {useGOT = 0;}
 
     /// addPassesToJITCompile - Add passes to the specified pass manager to
     /// implement a fast dynamic compiler for this target.  Return true if this

lib/Target/X86/X86TargetMachine.cpp

@@ -79,7 +79,7 @@ X86TargetMachine::X86TargetMachine(const Module &M,
     Subtarget(M, FS),
     FrameInfo(TargetFrameInfo::StackGrowsDown,
               Subtarget.getStackAlignment(), -4),
-    JITInfo(*this) {
+    JITInfo(*this), TLInfo(*this) {
   if (getRelocationModel() == Reloc::Default)
     if (Subtarget.isTargetDarwin())
       setRelocationModel(Reloc::DynamicNoPIC);
@@ -97,7 +97,7 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
       FileType != TargetMachine::ObjectFile) return true;
 
   // Run loop strength reduction before anything else.
-  if (EnableX86LSR) PM.add(createLoopStrengthReducePass());
+  if (EnableX86LSR) PM.add(createLoopStrengthReducePass(1, &TLInfo));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -164,6 +164,10 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   // The JIT should use static relocation model.
   TM.setRelocationModel(Reloc::Static);
 
+  // Run loop strength reduction before anything else.
+  if (EnableX86LSR)
+    PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering()));
+
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
 

lib/Target/X86/X86TargetMachine.h

@@ -17,18 +17,21 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/PassManager.h"
+#include "X86.h"
 #include "X86InstrInfo.h"
 #include "X86JITInfo.h"
 #include "X86Subtarget.h"
+#include "X86ISelLowering.h"
 
 namespace llvm {
 class IntrinsicLowering;
 
 class X86TargetMachine : public TargetMachine {
-  X86InstrInfo    InstrInfo;
+  X86InstrInfo      InstrInfo;
-  X86Subtarget    Subtarget;
+  X86Subtarget      Subtarget;
-  TargetFrameInfo FrameInfo;
+  TargetFrameInfo   FrameInfo;
-  X86JITInfo      JITInfo;
+  X86JITInfo        JITInfo;
+  X86TargetLowering TLInfo;
 public:
   X86TargetMachine(const Module &M, IntrinsicLowering *IL,
                    const std::string &FS);
@@ -37,6 +40,7 @@ public:
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
   virtual       TargetJITInfo    *getJITInfo()         { return &JITInfo; }
   virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
+  virtual       X86TargetLowering *getTargetLowering() { return &TLInfo; }
   virtual const MRegisterInfo    *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }