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https://github.com/c64scene-ar/llvm-6502.git
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Add a really quick hack at a machine code sinking pass, enabled with --enable-sinking.
It is missing validity checks, so it is known broken. However, it is powerful enough to compile this contrived code: void test1(int C, double A, double B, double *P) { double Tmp = A*A+B*B; *P = C ? Tmp : A; } into: _test1: movsd 8(%esp), %xmm0 cmpl $0, 4(%esp) je LBB1_2 # entry LBB1_1: # entry movsd 16(%esp), %xmm1 mulsd %xmm1, %xmm1 mulsd %xmm0, %xmm0 addsd %xmm1, %xmm0 LBB1_2: # entry movl 24(%esp), %eax movsd %xmm0, (%eax) ret instead of: _test1: movsd 16(%esp), %xmm0 mulsd %xmm0, %xmm0 movsd 8(%esp), %xmm1 movapd %xmm1, %xmm2 mulsd %xmm2, %xmm2 addsd %xmm0, %xmm2 cmpl $0, 4(%esp) je LBB1_2 # entry LBB1_1: # entry movapd %xmm2, %xmm1 LBB1_2: # entry movl 24(%esp), %eax movsd %xmm1, (%eax) ret woo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45570 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -157,6 +157,10 @@ namespace llvm {
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///
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FunctionPass *createMachineLICMPass();
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/// createMachineSinkingPass - This pass performs sinking on machine
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/// instructions.
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FunctionPass *createMachineSinkingPass();
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} // End llvm namespace
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#endif
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@ -29,6 +29,12 @@ static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
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cl::desc("Dump emitter generated instructions as assembly"));
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// Hidden options to help debugging
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static cl::opt<bool>
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EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
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cl::desc("Perform sinking on machine code"));
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FileModel::Model
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LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
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std::ostream &Out,
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@ -68,6 +74,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createMachineLICMPass());
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if (EnableSinking)
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PM.add(createMachineSinkingPass());
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// Perform register allocation to convert to a concrete x86 representation
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PM.add(createRegisterAllocator());
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206
lib/CodeGen/MachineSink.cpp
Normal file
206
lib/CodeGen/MachineSink.cpp
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@ -0,0 +1,206 @@
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//===-- MachineSink.cpp - Sinking for machine instructions ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-sink"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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STATISTIC(NumSunk, "Number of machine instructions sunk");
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namespace {
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class VISIBILITY_HIDDEN MachineSinking : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineFunction *CurMF; // Current MachineFunction
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MachineRegisterInfo *RegInfo; // Machine register information
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MachineDominatorTree *DT; // Machine dominator tree for the current Loop
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public:
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static char ID; // Pass identification
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MachineSinking() : MachineFunctionPass((intptr_t)&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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private:
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bool ProcessBlock(MachineBasicBlock &MBB);
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bool SinkInstruction(MachineInstr *MI);
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bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const;
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};
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char MachineSinking::ID = 0;
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RegisterPass<MachineSinking> X("machine-sink", "Machine code sinking");
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} // end anonymous namespace
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FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
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/// AllUsesDominatedByBlock - Return true if all uses of the specified register
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/// occur in blocks dominated by the specified block.
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bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
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MachineBasicBlock *MBB) const {
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assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs");
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for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg),
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E = RegInfo->reg_end(); I != E; ++I) {
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if (I.getOperand().isDef()) continue; // ignore def.
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// Determine the block of the use.
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MachineInstr *UseInst = &*I;
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MachineBasicBlock *UseBlock = UseInst->getParent();
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if (UseInst->getOpcode() == TargetInstrInfo::PHI) {
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// PHI nodes use the operand in the predecessor block, not the block with
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// the PHI.
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UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB();
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}
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// Check that it dominates.
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if (!DT->dominates(MBB, UseBlock))
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return false;
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}
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return true;
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}
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bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "******** Machine Sinking ********\n";
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CurMF = &MF;
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TM = &CurMF->getTarget();
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TII = TM->getInstrInfo();
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RegInfo = &CurMF->getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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bool EverMadeChange = false;
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while (1) {
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bool MadeChange = false;
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// Process all basic blocks.
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for (MachineFunction::iterator I = CurMF->begin(), E = CurMF->end();
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I != E; ++I)
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MadeChange |= ProcessBlock(*I);
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// If this iteration over the code changed anything, keep iterating.
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if (!MadeChange) break;
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EverMadeChange = true;
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}
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return EverMadeChange;
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}
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bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
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bool MadeChange = false;
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// Can't sink anything out of a block that has less than two successors.
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if (MBB.succ_size() <= 1) return false;
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// Walk the basic block bottom-up
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for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ){
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MachineBasicBlock::iterator LastIt = I;
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if (SinkInstruction(--I)) {
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I = LastIt;
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++NumSunk;
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}
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}
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return MadeChange;
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}
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/// SinkInstruction - Determine whether it is safe to sink the specified machine
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/// instruction out of its current block into a successor.
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bool MachineSinking::SinkInstruction(MachineInstr *MI) {
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// Loop over all the operands of the specified instruction. If there is
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// anything we can't handle, bail out.
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MachineBasicBlock *ParentBlock = MI->getParent();
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// SuccToSinkTo - This is the successor to sink this instruction to, once we
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// decide.
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MachineBasicBlock *SuccToSinkTo = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue; // Ignore non-register operands.
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (MRegisterInfo::isPhysicalRegister(Reg)) {
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// If this is a physical register use, we can't move it. If it is a def,
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// we can move it, but only if the def is dead.
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if (MO.isUse() || !MO.isDead())
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return false;
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} else {
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// Virtual register uses are always safe to sink.
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if (MO.isUse()) continue;
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// Virtual register defs can only be sunk if all their uses are in blocks
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// dominated by one of the successors.
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if (SuccToSinkTo) {
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// If a previous operand picked a block to sink to, then this operand
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// must be sinkable to the same block.
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if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo))
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return false;
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continue;
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}
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// Otherwise, we should look at all the successors and decide which one
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// we should sink to.
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for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(),
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E = ParentBlock->succ_end(); SI != E; ++SI) {
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if (AllUsesDominatedByBlock(Reg, *SI)) {
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SuccToSinkTo = *SI;
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break;
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}
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}
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// If we couldn't find a block to sink to, ignore this instruction.
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if (SuccToSinkTo == 0)
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return false;
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}
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}
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// FIXME: Check that the instr doesn't have side effects etc.
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DEBUG(cerr << "Sink instr " << *MI);
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DEBUG(cerr << "to block " << *SuccToSinkTo);
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// If the block has multiple predecessors, this would introduce computation on
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// a path that it doesn't already exist. We could split the critical edge,
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// but for now we just punt.
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if (SuccToSinkTo->pred_size() > 1) {
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DEBUG(cerr << " *** PUNTING: Critical edge found\n");
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return false;
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}
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// Determine where to insert into. Skip phi nodes.
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MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
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while (InsertPos != SuccToSinkTo->end() &&
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InsertPos->getOpcode() == TargetInstrInfo::PHI)
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++InsertPos;
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// Move the instruction.
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SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
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++MachineBasicBlock::iterator(MI));
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return true;
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}
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