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R600/SI: switch back to RegPressure scheduling

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Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-03-26 14:04:02 +00:00
parent f623008122
commit c53270f885
3 changed files with 9 additions and 1 deletions
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2
lib/Target/R600/SIISelLowering.cpp
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@ -74,7 +74,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setTargetDAGCombine(ISD::SETCC);
setSchedulingPreference(Sched::Source);
setSchedulingPreference(Sched::RegPressure);
}
SDValue SITargetLowering::LowerFormalArguments(

5
lib/Target/R600/SIRegisterInfo.cpp
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@ -30,6 +30,11 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const {
return RC->getNumRegs();
}
const TargetRegisterClass *
SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
switch (rc->getID()) {

3
lib/Target/R600/SIRegisterInfo.h
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@ -31,6 +31,9 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
/// \param RC is an AMDIL reg class.
///
/// \returns the SI register class that is equivalent to \p RC.