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Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and tell TTI about it so that popcount-loop recognition will know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
f464481db0
commit
c53ab4d77f
@ -61,6 +61,8 @@ def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction">;
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def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
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"Enable the popcnt[dw] instructions">;
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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@ -79,7 +81,6 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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// LFIWAX p6, p6x, p7 lfiwax
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// LFIWZX p7 lfiwzx
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// POPCNTB p5 through p7 popcntb and related instructions
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// POPCNTD p7 popcntd and related instructions
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// RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates
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// VSX p7 vector-scalar instruction set
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@ -131,12 +132,13 @@ def : ProcessorModel<"e5500", PPCE5500Model,
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def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureSTFIWX, FeatureISEL,
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Feature64Bit
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FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
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FeatureMFOCRF, FeatureFSqrt,
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FeatureSTFIWX, FeatureISEL,
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Feature64Bit /*, Feature64BitRegs */,
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FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */,
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FeatureQPX]>;
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def : Processor<"pwr3", G5Itineraries,
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[DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
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@ -160,7 +162,8 @@ def : Processor<"pwr6x", G5Itineraries,
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def : Processor<"pwr7", G5Itineraries,
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[DirectivePwr7, FeatureAltivec,
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FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
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FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;
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FeatureISEL, FeaturePOPCNTD, Feature64Bit
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/*, Feature64BitRegs */]>;
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def : Processor<"ppc", G3Itineraries, [Directive32]>;
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def : Processor<"ppc64", G5Itineraries,
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[Directive64, FeatureAltivec,
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@ -160,16 +160,22 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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// PowerPC does not have BSWAP, CTPOP or CTTZ
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setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
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if (Subtarget->hasPOPCNTD()) {
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setOperationAction(ISD::CTPOP, MVT::i32 , Promote);
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setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
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} else {
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setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
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setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
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}
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// PowerPC does not have ROTR
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setOperationAction(ISD::ROTR, MVT::i32 , Expand);
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setOperationAction(ISD::ROTR, MVT::i64 , Expand);
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@ -468,6 +468,9 @@ def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
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def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
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"cntlzd $rA, $rS", IntGeneral,
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[(set i64:$rA, (ctlz i64:$rS))]>;
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def POPCNTD : XForm_11<31, 506, (outs G8RC:$rA), (ins G8RC:$rS),
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"popcntd $rA, $rS", IntGeneral,
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[(set i64:$rA, (ctpop i64:$rS))]>;
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def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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"divd $rT, $rA, $rB", IntDivD,
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@ -40,6 +40,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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, HasFSQRT(false)
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, HasSTFIWX(false)
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, HasISEL(false)
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, HasPOPCNTD(false)
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, IsBookE(false)
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, HasLazyResolverStubs(false)
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, IsJITCodeModel(false)
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@ -79,6 +79,7 @@ protected:
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bool HasFSQRT;
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bool HasSTFIWX;
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bool HasISEL;
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bool HasPOPCNTD;
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bool IsBookE;
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bool HasLazyResolverStubs;
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bool IsJITCodeModel;
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@ -159,6 +160,7 @@ public:
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bool hasQPX() const { return HasQPX; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasPOPCNTD() const { return HasPOPCNTD; }
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bool isBookE() const { return IsBookE; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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@ -122,9 +122,8 @@ llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
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PPCTTI::PopcntSupportKind PPCTTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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// FIXME: PPC currently does not have custom popcnt lowering even though
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// there is hardware support. Once this is fixed, update this function
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// to reflect the real capabilities of the hardware.
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if (ST->hasPOPCNTD() && TyWidth <= 64)
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return PSK_FastHardware;
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return PSK_Software;
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}
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41
test/CodeGen/PowerPC/popcnt.ll
Normal file
41
test/CodeGen/PowerPC/popcnt.ll
Normal file
@ -0,0 +1,41 @@
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; RUN: llc -march=ppc64 -mattr=+popcntd < %s | FileCheck %s
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define i8 @cnt8(i8 %x) nounwind readnone {
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%cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
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ret i8 %cnt
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; CHECK: @cnt8
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; CHECK: rldicl
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; CHECK: popcntd
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; CHECK: blr
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}
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define i16 @cnt16(i16 %x) nounwind readnone {
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%cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
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ret i16 %cnt
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; CHECK: @cnt16
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; CHECK: rldicl
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; CHECK: popcntd
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; CHECK: blr
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}
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define i32 @cnt32(i32 %x) nounwind readnone {
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%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
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ret i32 %cnt
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; CHECK: @cnt32
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; CHECK: rldicl
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; CHECK: popcntd
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; CHECK: blr
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}
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define i64 @cnt64(i64 %x) nounwind readnone {
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%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
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ret i64 %cnt
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; CHECK: @cnt64
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; CHECK: popcntd
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; CHECK: blr
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}
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declare i8 @llvm.ctpop.i8(i8) nounwind readnone
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declare i16 @llvm.ctpop.i16(i16) nounwind readnone
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declare i32 @llvm.ctpop.i32(i32) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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