6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Fix an assertion caused by using inline asm with indirect register inputs.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2014-03-21 02:14:50 +00:00
parent 287cc35cd7
commit c53b3dbc20
2 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -6185,7 +6185,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
// types are identical size, use a bitcast to convert (e.g. two differing
// vector types).
MVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT;

16
test/CodeGen/ARM/inline-diagnostics.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: not llc %s -verify-machineinstrs -mtriple=armv7-none-linux-gnu -mattr=+neon 2>&1 | FileCheck %s
%struct.float4 = type { float, float, float, float }
; CHECK: error: Don't know how to handle indirect register inputs yet for constraint 'w'
define float @inline_func(float %f1, float %f2) #0 {
%c1 = alloca %struct.float4, align 4
%c2 = alloca %struct.float4, align 4
%c3 = alloca %struct.float4, align 4
call void asm sideeffect "vmul.f32 ${2:q}, ${0:q}, ${1:q}", "=*r,=*r,*w"(%struct.float4* %c1, %struct.float4* %c2, %struct.float4* %c3) #1, !srcloc !1
%x = getelementptr inbounds %struct.float4* %c3, i32 0, i32 0
%1 = load float* %x, align 4
ret float %1
}
!1 = metadata !{i32 271, i32 305}