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Remove the JustSP single-register regclass.

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It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93280 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-01-13 00:43:06 +00:00
parent 3aba5b1d60
commit c5b7ef1519
2 changed files with 1 additions and 14 deletions
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2
lib/Target/ARM/ARMInstrThumb.td
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@@ -113,7 +113,7 @@ def t_addrmode_s1 : Operand<i32>,
def t_addrmode_sp : Operand<i32>, def t_addrmode_sp : Operand<i32>,
ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
let PrintMethod = "printThumbAddrModeSPOperand"; let PrintMethod = "printThumbAddrModeSPOperand";
let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm); let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

13
lib/Target/ARM/ARMRegisterInfo.td
View File

@@ -367,19 +367,6 @@ def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
// Condition code registers. // Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
// Just the stack pointer (for tSTRspi and friends).
def JustSP : RegisterClass<"ARM", [i32], 32, [SP]> {
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
JustSPClass::iterator
JustSPClass::allocation_order_end(const MachineFunction &MF) const {
return allocation_order_begin(MF);
}
}];
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Subregister Set Definitions... now that we have all of the pieces, define the // Subregister Set Definitions... now that we have all of the pieces, define the
// sub registers for each register. // sub registers for each register.