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Convert some X86 blendv* intrinsics into IR.
Summary: Implemented an InstCombine transformation that takes a blendv* intrinsic call and translates it into an IR select, if the mask is constant. This will eventually get lowered into blends with immediates if possible, or pblendvb (with an option to further optimize if we can transform the pblendvb into a blend+immediate instruction, depending on the selector). It will also enable optimizations by the IR passes, which give up on sight of the intrinsic. Both the transformation and the lowering of its result to asm got shiny new tests. The transformation is a bit convoluted because of blendvp[sd]'s definition: Its mask is a floating point value! This forces us to convert it and get the highest bit. I suppose this happened because the mask has type __m128 in Intel's intrinsic and v4sf (for blendps) in gcc's builtin. I will send an email to llvm-dev to discuss if we want to change this or not. Reviewers: grosbach, delena, nadav Differential Revision: http://reviews.llvm.org/D3859 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209643 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -718,6 +718,41 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::x86_sse41_pblendvb:
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case Intrinsic::x86_sse41_blendvps:
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case Intrinsic::x86_sse41_blendvpd:
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case Intrinsic::x86_avx_blendv_ps_256:
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case Intrinsic::x86_avx_blendv_pd_256:
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case Intrinsic::x86_avx2_pblendvb: {
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// Convert blendv* to vector selects if the mask is constant.
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// This optimization is convoluted because the intrinsic is defined as
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// getting a vector of floats or doubles for the ps and pd versions.
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// FIXME: That should be changed.
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Value *Mask = II->getArgOperand(2);
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if (auto C = dyn_cast<ConstantDataVector>(Mask)) {
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auto Tyi1 = Builder->getInt1Ty();
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auto SelectorType = cast<VectorType>(Mask->getType());
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auto EltTy = SelectorType->getElementType();
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unsigned Size = SelectorType->getNumElements();
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unsigned BitWidth = EltTy->isFloatTy() ? 32 : (EltTy->isDoubleTy() ? 64 : EltTy->getIntegerBitWidth());
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assert(BitWidth == 64 || BitWidth == 32 || BitWidth == 8 && "Wrong arguments for variable blend intrinsic");
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SmallVector<Constant*, 32> Selectors;
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for (unsigned I = 0; I < Size; ++I) {
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// The intrinsics only read the top bit
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uint64_t Selector;
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if (BitWidth == 8)
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Selector = C->getElementAsInteger(I);
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else
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Selector = C->getElementAsAPFloat(I).bitcastToAPInt().getZExtValue();
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Selectors.push_back(ConstantInt::get(Tyi1, Selector >> (BitWidth - 1)));
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}
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auto NewSelector = ConstantVector::get(Selectors);
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return SelectInst::Create(NewSelector, II->getArgOperand(0), II->getArgOperand(1), "blendv");
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} else {
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break;
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}
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}
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case Intrinsic::x86_avx_vpermilvar_ps:
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case Intrinsic::x86_avx_vpermilvar_ps_256:
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case Intrinsic::x86_avx_vpermilvar_pd:
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@ -135,3 +135,26 @@ define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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}
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; If we can figure out a blend has a constant mask, we should emit the
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; blend instruction with an immediate mask
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define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
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; CHECK-LABEL: constant_blendvpd_avx:
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; CHECK-NOT: mov
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; CHECK: vblendpd
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; CHECK: ret
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab
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ret <4 x double> %1
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}
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define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
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; CHECK-LABEL: constant_blendvps_avx:
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; CHECK-NOT: mov
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; CHECK: vblendps
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; CHECK: ret
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd
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ret <8 x float> %1
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}
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
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declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
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11
test/CodeGen/X86/avx2-blend.ll
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11
test/CodeGen/X86/avx2-blend.ll
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@ -0,0 +1,11 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s
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define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
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; CHECK-LABEL: constant_pblendvb_avx2:
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; CHECK: vmovdqa
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; CHECK: vpblendvb
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%1 = select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %xyzw, <32 x i8> %abcd
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ret <32 x i8> %1
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}
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declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
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@ -88,3 +88,35 @@ entry:
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store double %extract214vector_func.i, double addrspace(1)* undef, align 8
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ret void
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}
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; If we can figure out a blend has a constant mask, we should emit the
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; blend instruction with an immediate mask
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define <2 x double> @constant_blendvpd(<2 x double> %xy, <2 x double> %ab) {
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; In this case, we emit a simple movss
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; CHECK-LABEL: constant_blendvpd
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; CHECK: movsd
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; CHECK: ret
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %xy, <2 x double> %ab
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ret <2 x double> %1
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}
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define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) {
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; CHECK-LABEL: constant_blendvps
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; CHECK-NOT: mov
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; CHECK: blendps $7
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; CHECK: ret
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %xyzw, <4 x float> %abcd
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ret <4 x float> %1
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}
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define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) {
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; CHECK-LABEL: constant_pblendvb:
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; CHECK: movaps
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; CHECK: pblendvb
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; CHECK: ret
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%1 = select <16 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <16 x i8> %xyzw, <16 x i8> %abcd
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ret <16 x i8> %1
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}
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declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>)
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declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>)
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56
test/Transforms/InstCombine/blend_x86.ll
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56
test/Transforms/InstCombine/blend_x86.ll
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@ -0,0 +1,56 @@
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; RUN: opt < %s -instcombine -mtriple=x86_64-apple-macosx -mcpu=core-avx2 -S | FileCheck %s
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define <2 x double> @constant_blendvpd(<2 x double> %xy, <2 x double> %ab) {
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; CHECK-LABEL: @constant_blendvpd
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; CHECK: select <2 x i1> <i1 true, i1 false>
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%1 = tail call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %xy, <2 x double> %ab, <2 x double> <double 0xFFFFFFFFE0000000, double 0.000000e+00>)
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ret <2 x double> %1
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}
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define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) {
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; CHECK-LABEL: @constant_blendvps
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; CHECK: select <4 x i1> <i1 false, i1 false, i1 false, i1 true>
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%1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000>)
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ret <4 x float> %1
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}
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define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) {
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; CHECK-LABEL: @constant_pblendvb
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; CHECK: select <16 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>
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%1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> <i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0>)
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ret <16 x i8> %1
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}
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define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
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; CHECK-LABEL: @constant_blendvpd_avx
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; CHECK: select <4 x i1> <i1 true, i1 false, i1 true, i1 false>
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%1 = tail call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %xy, <4 x double> %ab, <4 x double> <double 0xFFFFFFFFE0000000, double 0.000000e+00, double 0xFFFFFFFFE0000000, double 0.000000e+00>)
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ret <4 x double> %1
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}
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define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
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; CHECK-LABEL: @constant_blendvps_avx
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; CHECK: select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>
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%1 = tail call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %xyzw, <8 x float> %abcd, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0xFFFFFFFFE0000000>)
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ret <8 x float> %1
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}
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define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
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; CHECK-LABEL: @constant_pblendvb_avx2
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; CHECK: select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>
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%1 = tail call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %xyzw, <32 x i8> %abcd,
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<32 x i8> <i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0,
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i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0,
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i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0,
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i8 0, i8 0, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0>)
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ret <32 x i8> %1
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}
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declare <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8>, <16 x i8>, <16 x i8>)
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declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>)
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declare <2 x double> @llvm.x86.sse41.blendvpd(<2 x double>, <2 x double>, <2 x double>)
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declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
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declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
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