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Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.

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PR9650
rdar://problem/9257565


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-08 19:41:22 +00:00
parent 40de2b3f15
commit c636074afc
2 changed files with 13 additions and 9 deletions
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19
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -532,17 +532,18 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
switch (Opcode) { switch (Opcode) {
default: default:
// Did we miss an opcode? // Did we miss an opcode?
assert(0 && "Unexpected opcode!"); DEBUG(errs() << "BadRegsMulFrm: unexpected opcode!");
return false; return false;
case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT:
case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT:
case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8: case ARM::SMMLA: case ARM::SMMLAR: case ARM::SMMLS: case ARM::SMMLSR:
case ARM::USADA8:
if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
return true; return true;
return false; return false;
case ARM::MUL: case ARM::SMMUL: case ARM::SMULBB: case ARM::SMULBT: case ARM::MUL: case ARM::SMMUL: case ARM::SMMULR:
case ARM::SMULTB: case ARM::SMULTT: case ARM::SMULWB: case ARM::SMULWT: case ARM::SMULBB: case ARM::SMULBT: case ARM::SMULTB: case ARM::SMULTT:
case ARM::SMUAD: case ARM::SMUADX: case ARM::SMULWB: case ARM::SMULWT: case ARM::SMUAD: case ARM::SMUADX:
// A8.6.167 SMLAD & A8.6.172 SMLSD // A8.6.167 SMLAD & A8.6.172 SMLSD
case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX: case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX:
case ARM::USAD8: case ARM::USAD8:
@ -562,14 +563,14 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
} }
// Multiply Instructions. // Multiply Instructions.
// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLAR,
// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience): // SMMLS, SMMLAR, SMLAD, SMLADX, SMLSD, SMLSDX, and USADA8 (for convenience):
// Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
// But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is // But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is
// only for {d, n, m}. // only for {d, n, m}.
// //
// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX, // MUL, SMMUL, SMMULR, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD,
// USAD8 (for convenience): // SMUADX, and USAD8 (for convenience):
// Rd{19-16} Rn{3-0} Rm{11-8} // Rd{19-16} Rn{3-0} Rm{11-8}
// //
// SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT,

3
test/MC/Disassembler/ARM/arm-tests.txt
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@ -278,3 +278,6 @@
# CHECK: uqsax r5, r6, r7 # CHECK: uqsax r5, r6, r7
0x57 0x5f 0x66 0xe6 0x57 0x5f 0x66 0xe6
# CHECK: smmlareq r0, r0, r0, r0
0x30 0x00 0x50 0x07